面議(經常性薪資達4萬元或以上) 新竹市東區 10年工作經驗 6天前更新
1.Ownership of SRAM bit-cells for all technology extensions.
2.Own and co-optimize competitive SRAM devices to meet electrical, and reliability specifications at optimum yield levels.
3.Clear understanding of SRAM bit-cell design, electrical test structures, test conditions, and familiar with layout optimization techniques.
4.Design layout and experiments dedicated to the continuous SRAM development for leading-edge CMOS technologies.
5.Interface with device and integration teams on cross-functional issues affecting SRAM related performance, yield, or reliability impacting products.
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