面議(經常性薪資達4萬元或以上) 台北市中山區 工作經歷不拘 731天前
職責要求
- RTL/Logic Integration and Verification
- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC.
- Use cdc tool to check RTL/SDC quality
- Hands-on experience on post-silicon debug
任職資格
- Knowledge and design experience of digital flows & FPGA validations
- One of the Key Serdes protocol (PCIe, SATA, USB, VBO, MIPI etc.)
- Knowledge and design experience of PCS
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