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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 月薪30000~40000元 新竹縣竹北市 工作經歷不拘 1天前展開
1.處理產品之客戶訂單與進度追蹤 2.協助整理產品規格與文件編輯 3.回覆客戶產品之詢價與需求 4.統籌安排產品出貨事宜及物流追蹤 5.支援業務相關交辦事項，如資料彙整與提案撰寫 6.協助內部產品資料歸檔與維護更新
產假年終獎金員工聚餐尾牙勞保 - 月薪28590~30000元 台南市新市區 工作經歷不拘 1天前展開
1.配合度高 2.學習力強 3.執行主管交辦事務 4.基本電腦操作 5.數據分析能力佳 6.須配合工廠作業程序 7.辦公室文書作業
全勤獎金年節獎金伙食津貼勞保健保 - 月薪37000~48000元 新竹市東區 工作經歷不拘 1天前展開
1、機械設備 檢測/ 測試 / 維修，有學長帶著做 2、自動化傳輸設備保養、維修、解異常、調整以及各項客戶交辦事項~ 3、穩定成長！ 無經驗可，完整培訓 4、初期常日班，未來依產能狀況調整為做三休三 5、台積電新廠房，進階跳板管道
- 時薪210~250元 台北市內湖區 工作經歷不拘 1天前展開
1.不需跟專職輔導老師一樣，但也要有部分輔導解題能力 2.行政助理，協助櫃檯老師排課派課、現場管理 福利：有全勤獎金、有代班獎金、可免費參加每次段考同樂會用餐、可免費參加尾牙。
三節獎金不用補班員工在職教育訓練良好升遷制度 - 時薪210~250元 台北市內湖區 工作經歷不拘 1天前展開
1.不需跟專職輔導老師一樣，但也要有部分輔導解題能力 2.行政助理，協助櫃檯老師排課派課、現場管理 福利：有全勤獎金、有代班獎金、可免費參加每次段考同樂會用餐、可免費參加尾牙。
三節獎金不用補班員工在職教育訓練良好升遷制度 - 面議（經常性薪資達4萬元或以上） 新竹縣寶山鄉 工作經歷不拘 1天前展開
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16565&source=1111&tags=AO+2026_1111 Description : R&D Engineers will be part of a grand joint-force working on advanced technologies, including but not limited to exploratory research in advanced device architecture, market-oriented design IP enablement, device and process integration for manufacturability, package-level interconnect solutions, and novel material/equipment/process evaluations. Responsibilities: 1. Research & Pathfinding (1) New material and new process pathfinding to enable new device architecture with integration. (2) New tool pathfinding for new materials to enable the next nodes. (3) Design, execute and analyze experiments to meet R&D engineering specifications. (4) Process stability & manufacturability improvement for yield and reliability qualification. (5) Process/tool transfer to development R&D or volume manufacturing (Fab). (6) Highly motivated individuals with a strong technical background and teamwork skills. 2. Integration (1) Technology definition: design rules, design-technology co-optimization, logic/memory IP evaluations, etc. (2) Technology development infrastructure: productivity enhancement, product inspection methodology, mask-making, and test flow, etc. (3) New test vehicle establishment and validation: improvement of device yield and reliability (learning cycles). Improve yield and reduce defects by quantifying defect attributes using programming skills and developing effective detection methodologies. (4) Customer design enablement: SPICE Modeling and IP qualifications. 3. Module (1) Develop advanced processes, materials, tools, models, and computational methodologies for leading edge technologies. (2) Deliver manufacturable, stable, cost-effective technologies with device performance improvement for yield and reliability qualification. (3) Transfer process and tool to high volume manufacturing fab. 4. R&D Process Center (1) PE: Advanced module process development and baseline sustaining. (2) EE: Handle advanced equipment at R&D stage. Install, warm up, sustain and troubleshooting solve with new technology equipment. (3) MFG: Oversee the daily operations of IC foundry to ensure that all profiling operations, workflow, and customer reports are consistent with agreed upon service operations.
- 月薪30000~40000元 新竹縣竹北市 工作經歷不拘 1天前展開
1. 協助進行電路板設計布局，優化電子元件位置與連接路徑。 2. 支援通訊相關設備的測試與故障排除，提供技術建議。 3.執行光電模組產品測試流程並整理測試報告 4.協助製作生產流程文件及完善技術資料 5.準備與編寫技術報告，並進行相關文件歸檔管理。 6.執行主管交辦的工程相關事項，及時反饋進度與問題。
產假年終獎金員工聚餐尾牙勞保 - 1111南台灣職場小語
【推薦工作】行政內勤、行政助理｜無經驗可，享週休二日！
- 月薪32000元 台北市中正區 工作經歷不拘 1天前展開
1. 客戶關係管理：負責與客戶溝通、維護並建立良好的合作關係，提供快速且精確的回應。 2. 行政庶務處理：協助文件整理、資料輸入以及內部數據更新，確保資料準確性。 3. 業務支援：負責訂單處理與追蹤，確保供應鏈中各環節順暢運作。 4. 溝通與協調：與內外部團隊合作解決問題，促進工作流程的順利進行。 5. 資料分析與報告：收集並整理營運數據，撰寫分析報告供決策參考。 6. 活動協助：協助內部會議與活動的安排，確保活動順利進行。 7. 供應商聯繫：負責與供應商洽談，確認採購進度，保障物料供應。 8. 時間管理：有效安排工作時程，協助主管分配每日工作優先級。
就業保險員工生日禮金年終獎金激勵獎金績效獎金 - 面議（經常性薪資達4萬元或以上） 新竹縣寶山鄉 工作經歷不拘 1天前展開
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16566&source=1111&tags=AO+2026_1111 Description : At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. Responsibilities: 1. Physical Designer The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 2. Standard Cell Engineer (1) Pathfinding of library characterization for leading edge tech nodes. (2) Support industrial standard library kits generation and QC. (3) In-house library generation flow and/or utility development. (4) RC parasitic extraction analysis and APR related analysis. 3. Layout Engineer (1) IC layout for advanced technology (Std. cell/Memory/AMS/IO). (2) Layout structure development for new technology. (3) Pathfinding for new technology development. (4) Customer engagement and layout support. (5) Design and technology co-optimization (DTCO). (6) AI and automation for layout and physical design. 4. System and Chip Design Solutions Development Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 5. FE design & DFT (1) Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG). (2) Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. (3) Technology benchmarking for PPA evaluation of the advanced nodes. (4) DTCO (Design & Technology Co-Optimization) pathfinding and development. 6. SRAM Engineer (1) SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. (2) RRAM/MRAM, emerging memory development. (3) In memory computing research and development. 7. Design Flow/Methodology (1) Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support. (2) Advanced technology design development flow development and technical support. (3) Automation program development to support design kits and flow development productivity/quality.
- 月薪55000元 桃園市楊梅區 工作經歷不拘 1天前展開
1、工程發包採購作業(詢價、比價、議價) 2、廠商資料、建材及型錄等整理與歸檔 3、工地及廠商之間溝通與協調 4、開發新廠商、資料庫建立與維護 5、主管交辦事項
產假產檢假安胎假家庭照顧假年終獎金 - 月薪30000元 台中市沙鹿區 工作經歷不拘 1天前展開
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自強活動員工聚餐勞保健保週休二日 - 面議（經常性薪資達4萬元或以上） 新竹縣寶山鄉 工作經歷不拘 1天前展開
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16567&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1. Novel devices developing for specialty technology. 2. Device Simulation, Test-chip design tape out and measurement system developing. 3. Process flow developing for production. 4. Collaborate with related teams for Design Collaterals (DRM/DRC/LVS/SPICE/PDK) developing.
- 面議（經常性薪資達4萬元或以上） 新竹縣寶山鄉 工作經歷不拘 1天前展開
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16568&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: As a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer‘s variety applications. 1. Integration (1) Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline. (2) Package level reliability, failure mode analysis and improvement plan. (3) Customer technical interface, new tape out and lot handle. (4) Handover developed technologies to manufacturing groups for production. 2. Module Development (1) Be responsible for CVD/PVD/CMP/Lithography/Etch/Polymer/Bonding/Clean module development for 3DIC projects. (2) New technology, materials survey, and process improvement on 3DIC package structures. (3) Process development and tool transfer to mass-production development. 3. Simulation (1) Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment. (2) Practice FEM and DOE in problem solving and path finding particularly on packaging. (3) Continue improvement in simulation methodology, material modeling and script automation.
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