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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 26天前更新展開
1. Conduct market/technology trend analysis and customer/product requirements for technical roadmap planning 2. Guide the SoC development with (AI) technical background, and collaborate with engineering/marketing teams and 3rd parties for Key features promotion, landing and marketing
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 26天前更新展開
1. WiFi/BT 電路系統分析、IC驗證除錯、公板製作、數據蒐集及分析 2. PCB公版設計, 除錯 3. EMI 防治對策 4. 高速數位介面應用及除錯 5. 客戶支持
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 26天前更新展開
1. Define the roadmap and product portfolio of tablet, eReader, OTT, smart display and wearable. Drive product positioning and value propositions. 2. GTM strategy planning and execution, win design awards, and deliver revenue. 3. Customer engagement and relationship build up. 4. Collaborate closely with internal RD, PM team to understand product architecture, roadmap, and differentiating features, ensuring marketing deliverables are technically accurate. 5. Work with sales teams to support customer engagements, respond to technical inquiries, and drive product adoption.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 26天前更新展開
1. Processor core, cache and peripheral verification 2. Verification flow and methodology 3. Advanced tool and verification technology survey
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 26天前更新展開
1) 軟體層面的 Android 系統整合 2) Linux 系統軟體開發 3) Linux Kernel Driver開發
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 3年工作經驗 26天前更新展開
1. HSI IP development 2. Short term: Help integration of on-going project including QC. 3. Long term: Deep learn into 3rd party HSI IP. Know the detailed spec of PCIe/UCIE/USB4 and able to co-work with DV.
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 26天前更新展開
1. 設計、開發和維護多媒體應用程式，包括但不限於Video playback, Image, playback。 2. 開發和優化 Android 平台上的多媒體應用程式，確保其性能和穩定性。 3. 開發和維護嵌入式系統上的多媒體應用程式，確保其在資源受限環境中的高效運行。 4. 與設計師、產品經理和其他工程師合作，確保多媒體應用程式的功能和使用者體驗達到高標準。 5. 進行多媒體技術的研究和創新，持續改進現有產品的性能和功能。 6. 撰寫和維護技術文件，確保程式碼的可讀性和可維護性。 7. 參與產品測試和除錯，確保產品的穩定性和可靠性。 8. 依據市場需求和用戶反饋，進行產品的優化和升級。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 26天前更新展開
1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 26天前更新展開
1. Develop Ethernet MAC for HPC networking applications. 2. Work closely with architecture, verification and physical teams from specification to implementation.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 4年工作經驗 26天前更新展開
1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 8年工作經驗 26天前更新展開
1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 26天前更新展開
【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
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