- 月薪32000~55000元 台北市內湖區 2年工作經驗 21天前更新展開
【工作內容】 1. 處理動態特效所需之拆件、骨架權重綁定 2. 遊戲專案之角色動態製作 【必備條件】 1. 熟悉 Spine2D、After Effect、Photoshop 等軟體 2. 重視溝通、責任及團隊合作，積極主動學習 3. 具備基本動態設計能力及創造力 4. 需附上相關作品集或作品網址 【加分項目】 1. 具成人遊戲美術製作經驗者佳 2. 具SLOT GAME美術相關經驗者佳
員工生日禮金年終獎金三節獎金員工團保國內旅遊 - 時薪197~242元 台北市中山區 工作經歷不拘 3天前更新展開
【外賣員】 工作內容：準備販賣的飲料、餐點販賣、整理清潔、販賣完畢食材及收取金額需交由值班主管盤點 工作時間：06:00~10:00 ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––- 工作地點：中山捷運站 相關福利：享保險、免費制服、員工優惠餐飲等。 PS：用餐時段因店內忙碌，請勿來電，謝謝。 【–MOS漢堡歡迎您的加入–】
員工及眷屬喪葬補助員工購物優惠需穿著員工制服員工在職教育訓練良好升遷制度 - 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 42天前更新展開
We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 42天前更新展開
1.Develop fault simulation flow for function safety. 2.Deploy fault simulation for safety IPs 3.Co-work with IP design verification teams to achieve pre-silicon verification of hardware safety requirements
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 42天前更新展開
1.Collect the safety design spec for the camera/display/audio subsystem and build the execution plan for safety design verification 2.Co-work with IP design verification teams to achieve pre-silicon verification of hardware safety requirements 3.Deploy fault simulation for safety IPs
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 42天前更新展開
1.Digital design (RTL design, Synthesis, integration, verification) 2.SoC Chip design, integration 3.Familiar with VLSI design flow is a plus
- 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 42天前更新展開
1. Responsible for the development of soft firmware of ASIC product system, high-speed data transmission Software/PHY development and optimization of hardware performance 2. Lead related IP development, familiar with software/firmware/SDK, issue debugging, optimization and testing in ASIC projects 3. Collaborate with the team for functional/system bring-up, validation, performance optimization and adjustment 4. Achieve product design-in import and support product mass production 5. It would be better if being capable in Signal Processing/Algorithm implementation and SI/PI simulation interpretation.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 42天前更新展開
1. 車用客戶品質窗口，負責前期品質相關討論(APQP,RFQ,PPAP..etc)與量產品質持續改善 2. 負責車用客戶異常退貨分析與溝通 3. 協助車用客戶生產品質改善 4. 推動內部品質系統流程精進
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 42天前更新展開
1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 42天前更新展開
1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 42天前更新展開
1. Implement and maintain device drivers, or firmware for high-speed interfaces, such as PCI Express, MIPI CSI-2, USB or UFS. 2. Develop FuSa and security software framework for high-speed interfaces to fulfill automotive requirements.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 42天前更新展開
1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 42天前更新展開
We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. Roles: 1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.
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