- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 88天前更新展開
• Work with the architecture team in the early stage of the project to derive various architecture and micro-architecture proposals. • Work with the performance architect to create performance models for various functional blocks of a microprocessor, memory subsystem and the whole core. • Work with design teams to analyze performance corner cases and provide feedback to the architecture team.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 88天前更新展開
Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 88天前更新展開
Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 88天前更新展開
• Define GPU compiler software architecture and interfaces. • Development/implement GPU compiler pipeline, linking and various optimizations/transformations. • Collaborate with Driver team, HW team to implement new API & HW features. • Collaborate with Driver team, HW team to improve/tune performance & power consumption. • Execute & deliver to meet milestones/schedules. • Analyze and debug code generation issues. • Construct reliable & trustable relationships across teams internally & externally.
- 面議（經常性薪資達4萬元或以上） 台北市中山區 1年工作經驗 2天前更新展開
1、數位收付整合服務審核作業。 2、數位收付、繳費稅相關帳務作業。 3、數位收付營運及帳務流程優化改善建議。 4、跨部門溝通協調、協助處理數位收付營運作業問題。 5、協助防洗風控相關報表作業。 6、落實個資保護及完成主管交辦事項。
年節獎金員工生日禮金年終獎金禮品員工團保 - 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 88天前更新展開
負責開發5G SOC的軟/韌體並讓產品量產 1. 開發/Porting/優化5G晶片的軟/韌體 2. 開發/維護 5G 網通/網卡/模組等相關功能
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 88天前更新展開
1. CPU Architect 2. CPU Performance Architect 3. CPU Design Verification Lead
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 88天前更新展開
1. 架構和數位電路設計 2. RTL實做和驗證 3. SoC chip整合和RTL到gate level實現, 包含timing分析跟量產測試 4. 設計方法和整合流程改善
- 月薪35000~38000元 新北市土城區 工作經歷不拘 3天前更新展開
1.產品異常應用工況處理 2.提供客戶產品技術諮詢 3.家戶水表儀表設備故障查修、更換 4.現場技術支援 5.主管交辦事項 *無經驗可
需穿著員工制服員工在職教育訓練全勤獎金年節獎金員工生日禮金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 89天前更新展開
1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 89天前更新展開
跨團隊合作(如:數位設計,系統應用, 測試, 製程...)以最佳化系統單晶片/平台競爭力及效能 ‧ 基於類比設計技術背景, 與類比設計團隊合作提供混合信號解決方案或IP, 以最佳化系統單晶片/平台競爭力及效能. 於計畫開發過程中, 協調類比團隊共同解決相關問題及克服挑戰, 以達成量產目標
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