- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 5天前更新展開
1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.
- 月薪30000~35000元 新竹縣竹北市 工作經歷不拘 5天前更新展開
★工作內容：產線製程/鍍膜/清潔 等製程作業 ★須早/中輪班 早班上班時間：08:30-17:30 中班上班時間：16:30-01:00 【自我推薦獎金】 即日起，主動應徵本職缺，並到職滿三個月(試用過後成為正職員工)，可得獎金6,000元。 獎勵期間自即日起至2025/12/31，視招募情況可提前結束。
就業保險產假產檢假安胎假家庭照顧假 - 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 5天前更新展開
1. 優化數位 IC 設計流程與方法 (使用 AI) 2. 執行與管理數位 IC 設計 EDA 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 使用 AI 或 EDA 工具針對 PPA（Performance, Power, Area）進行優化 4. 將依應徵者的年資與專業經驗，提供不同的職級
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 5天前更新展開
1. 資料中心AI晶片架構設計與RTL實作 2. 資料中心SoC與AI運算平台設計與驗證 3. 系統匯流排與AI週邊設計 4. SoC系統效能分析
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 4年工作經驗 5天前更新展開
- 針對下一代資料中心產品，推動並導入 SoC 層級的先進功耗優化技術；與 RTL、合成與布局團隊協作，完成低功耗功能的架構規劃與導入。 - 於各設計階段（RTL → 閘級 → 佈局後）進行功耗估算與分析，提出可執行的省電建議與改善方向。 - 與 Tier-1 客戶合作制定功耗規格，並提供下一代產品的功耗估算結果與技術說明。 - 支援樣品回片後的功耗量測比對（silicon correlation）與功耗相關問題除錯（sample back / bring-up）。
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 6年工作經驗 5天前更新展開
- 透過推動跨部門在技術需求、介面定義與交付項目上的一致性，協調先進封裝解決方案的開發（例如 CoWoS、2.5D/3.5D 整合，以及 Chiplet 架構）。 - 主導 SoC Floorplanning 以最佳化 PPA（功耗、效能與晶片面積），並在時序收斂、繞線壅塞、電源域邊界，以及 PDN／熱設計等考量間取得平衡。 - 與封裝團隊合作制定並優化 Ball/Bump 配置（bump/ball map），以滿足 SI/PI、電流承載能力、可製造性與可靠度等需求。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 5天前更新展開
1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 5天前更新展開
1. SoC low power design, integration, and modeling 2. SoC adaptive voltage scaling development
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 5天前更新展開
Role Summary: We are seeking a Principal Product Engineer to support advanced optical product development, NPI, manufacturing transfer, production ramp, and sustaining engineering in Taiwan. This is a senior individual contributor role requiring deep hands-on experience in fiber optics, optical module manufacturing, process integration, yield improvement, and cross-functional execution with engineering, operations, quality, supply chain, and contract manufacturing teams. The ideal candidate will serve as a technical lead for optical product engineering in Taiwan, helping drive products from development builds through qualification, pilot production, and high-volume manufacturing. Key Responsibilities: • Lead product engineering execution for optical products from prototype builds through qualification, production release, and sustaining support. • Support NPI planning, engineering builds, manufacturing readiness, test readiness, process transfer, and ramp execution. • Drive technical issue resolution across optical assembly, fiber attach, process integration, module test, final test, reliability, and customer quality. • Work closely with design engineering, optical engineering, packaging, test, reliability, operations, quality, and supply chain teams. • Partner with contract manufacturers and suppliers to resolve yield, quality, process, material, and production ramp issues. • Lead data-driven yield improvement using production data, failure pareto analysis, root-cause investigation, corrective action, and process optimization. • Support development and release of optical assembly and fiber attach processes, including process flows, control plans, inspection criteria, process windows, and manufacturing release criteria. • Provide technical leadership for product characterization, margin analysis, failure analysis, reliability learning, and production excursion response. • Help define manufacturing specifications, test limits, outgoing quality controls, and product-level production metrics. • Support customer or supplier technical escalations related to product quality, manufacturing performance, or reliability.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 5天前更新展開
We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 5天前更新展開
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 5天前更新展開
此職位高度重視執行力、組織協調以及所有ASIC設計的準時交付。 該職位負責協調涵蓋設計、驗證、PD、測試、DFT、封裝測試、營運和供應鏈等多個領域的複雜跨學科工作。 專案經理確保所有內部團隊從概念到生產全程保持一致，同時識別並克服所有風險和跨職能依賴關係。 This role is highly focused on execution excellence, organizational alignment and on-time delivery of all ASIC designs. This role coordinates complex multi-disciplinary efforts spanning, Design, Verification, Physical Design, Test Vehicles, DFT, Packaging Test, Operations and supply chain. The program manager insures that all internal groups are aligned from concept through production while identifying and overcoming all risks and cross functional dependencies.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 5天前更新展開
－Product marketing, planning, and strategy for AI data center products (e.g., Server CPU, AI accelerators/XPU, switch/networking products, optical interconnect) －Product lifecycle management, from ideation and requirements definition through development, launch, go-to-market, and end-of-life －Proactively identify new market opportunities and initiate new product concepts based on market trends, customer pain points, competitor analysis, and technology evolutions. －Develop and communicate clear value propositions and product stories that resonate with customers, stakeholders, and executive leadership. －Drive cross-functional alignment with engineering, business development, marketing, and support teams to successfully deliver and launch products. －Conduct deep market and competitive analysis to inform product strategy, pricing, and positioning. －Engage with key customers, industry leaders, and ecosystem partners to gather feedback, validate product ideas, and drive adoption.
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 5天前更新展開
1. 設計、開發和維護安全啟動（Secure Boot）系統和引導加載程序（Bootloader）。 2. 實施和優化安全措施，包括密鑰管理、數字簽名和加密技術。 3. 與硬體工程師緊密合作，以確保驅動程式與硬體設計的兼容性。 4. 整合應用端的技術要求，與應用開發團隊合作，確保 secure IP 驅動程式的順利整合。 5. 進行安全漏洞分析，並提出相應的緩解策略。
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