- 月薪40000~75000元 新竹縣新豐鄉 工作經歷不拘 9天前更新展開
(1)Probe Card MLO/Carrier載板案件製造評估。 (2)與製造單位溝通廠內DFM(製程能力表)。 (3)疊構設計評估。 (4)BGA Pin Definition評估 (5)高速訊號/一般IO/電源 Layout Routing (6)BOM及Gerber產出。 *無經驗可(有MLO/載板設計經驗或有濃厚興趣者尤佳)。 *有Allegro Orcad/PCB Designer/APD+/CAM軟體操作經驗一年以上者優先面談。 *有PISI模擬經驗者優先面談 *細心沉穩、配合度高、情緒管理能力好、學習意願高者尤佳。 日班 08:30-17:30/中班 13:00-21:30 班別可選擇
就業保險員工生日禮金家庭照顧假產假產檢假 - 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 31天前更新展開
1. Burn in process flow set up & qualification plan 2. Qualification failure electrical & physical analysis 3. Product reliability concern engagement with customer 4. New test supplier audit & qualification 5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.) 6. New product/technology introduction quality & reliability management 7. Testing house supplier quality improvement project
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 31天前更新展開
1) 移植及建置Linux/Android/Yocto系統與相關軟體至既有SoC平台 2) 負責IC模組驗證，平台開機問題分析與解決 3) 建構及優化Booting流程 4) 系統分析與效能改善 5) 記憶體管理優化任務
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 31天前更新展開
Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 31天前更新展開
1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 31天前更新展開
Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 31天前更新展開
1. 與業務使用者進行需求訪談與流程討論 2. IT 相關服務的專案管理 3. 公司商務領域的數位化（應用系統、人工智慧、數據）轉型 1. Engagement and Process Discussion with Business Users. (FIN domain) 2. Project Management on IT Service 3. Digitalization (application, AI, data) Transformation for business domain
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 31天前更新展開
1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 31天前更新展開
-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 -建立並維護測試平台，進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果，協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板，支援系統驗證。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 31天前更新展開
As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan. It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan Work location: Hsinchu/Taipei
- 月薪41000~80000元 桃園市龜山區 2年工作經驗 9天前更新展開
1. 政策管理： ● 執行資訊安全相關稽核作業 ● 資安事件、漏洞缺失追蹤與改善 ● 資訊安全政策相關文件統整與維護 ● 資安教育訓練與資安宣導 2. 技術管理： ● 資訊安全相關專案追蹤與規劃 ● 風險評估執行與彙整
就業保險員工生日禮金家庭照顧假產假產檢假 - 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 31天前更新展開
1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development 3. Common strip format unification management 4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) 5. PCB technology development and DRM owner
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