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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 台北市信義區 2年工作經驗 1天前更新展開
我們正積極尋找對數據分析、客戶洞察及數據應用有高度興趣的夥伴加入。 作為數據分析與數位策略團隊的一員，你將參與網站流量、客戶行為、交易資料及行銷數據之整合與分析，協助建立數據追蹤與資料應用機制，透過數據洞察協助平台、內容及行銷策略優化進而幫助公司決策。 －【數據整合與分析機制建置】： 負責網站流量、使用者行為、平台數據、行銷成效及交易相關資料之整合與分析，建立數據追蹤、分析及成效監測機制。 －【客戶資料與數據應用規劃】： 協助建立客戶資料庫、數據分析架構及資料應用邏輯，透過客戶行為、交易數據及平台使用狀況進行客戶洞察與分群分析。 －【跨部門數據協作與資料需求規劃】： 與資訊單位協作進行資料需求規劃、數據欄位整理及資料串接，逐步建立可供分析與決策使用之數據資料架構。 －【數據洞察與優化建議】： 依據數據分析結果，提出平台功能、內容經營、行銷活動及客戶經營方向之優化建議，協助提升平台使用成效與行銷轉換表現。 －【數據視覺化與分析報表】： 規劃數據視覺化儀表板、分析報表及數據監測機制，協助主管及團隊掌握數據變化與經營成效。 －【廠商管理與其他作業】：負責廠商聯繫與管理、合約審閱與修正，並處理例行行政事項及主管交辦任務。
就業保險產假眷屬團保誤餐費伙食津貼 - 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 今天剛更新展開
1. CPU system design, Power, performance and Area analysis 2. MCUSYS u-Architecture design 3. AMBA System bus architecture and integration
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 今天剛更新展開
1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
1. SoC Safety Island 的設計、整合與建模 2. SoC 功能安全的分析、設計、整合與建模 3. SoC 系統安全與性能分析 4. 汽車／智慧型手機晶片的架構設計與 RTL 實作
- 月薪45000~57000元 新北市泰山區 3年工作經驗 8天前更新展開
1. 協助新產品之研究、開發與測試驗證。 2. 執行產品性能分析、問題排除及改善方案評估。 3. 跨部門協調與專案執行。 4. 配合公司培訓計畫，逐步提升產品研發與管理能力。 培訓與發展 1. 完整的教育訓練與導師制度。 2. 產品研發專業技能培養。 3. 專案執行與跨部門溝通能力養成。 4. 未來可晉升為產品開發計劃經理、產品開發專案經理、研發主任工程師或技術管理職位。
員工電影國內旅遊員工聚餐尾牙家庭日 - 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 8天前更新展開
熟悉 layout tool : Virtuoso/CustomCompiler verification : Hercules/calibre/ICV 『具工作經驗者，薪資另議』
員工電影國內旅遊員工聚餐尾牙家庭日 - 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 3天前更新展開
The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 3天前更新展開
***Please upload English resume onto our official platform: https://reurl.cc/9WEqOV NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries. Opportunity Join a world class team working on state of the art Tier 1 automotive products. NXP‘s Highly Profitable Business Line Advanced Power Solutions is seeking experienced Mobile Power Analog Designers. We engage directly with the most visible and successful mobile companies. Site Job Description Working in the Power Delivery group of the Advanced Power Solutions business line, candidate will be part of a team developing fast charging and power delivery solutions for mobile applications. Task and responsibilities - Responsible for technical executions from block design, verification, and validation for mixed signal integrated circuits, Guarantee the technical deliverables of his jobs in terms of quality and performance; - This includes system definition, block architecture, circuit design, simulation and layout. All aspects require good engineering skills together with analysis, creativity, collaboration and customer interaction. - Must have strong expertise in analog design theory and device physics, and be capable of applying these to original and novel techniques that can provide significant value. - Write articles for technical publications and conferences, and provide email and phone support for assigned products. - Documentation for design reviews and design notes, layout guidance, and other cell design activities. - Our work culture encourages engineering innovation and creativity. Engineers are expected to file patents, publish papers or technical articles and to maintain awareness of current technical developments. Design engineers are part of a team and interact globally and locally with customers, design partners, product, test and packaging engineers, program management, quality, and business teams. Qualifications - Candidate needs to hold a minimum of a B.S. degree in electrical engineering. M.S. degree is preferred. - At least 10 years direct experience designing analog and mixed-signal transistor level circuitry for power management applications. - Ability to design traditional analog MOS and BJT circuits such as bandgap references, amplifiers, oscillators, detection circuits, linear LDO and switching regulators. - Ability to design multiphase DC-DC switching converter and experienced in current balance circuit. - Knowledge in digital controlled loop design. - Other desirable skills include experience with mixed-signal design tools and flow, reading and writing Verilog AMS models.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 3天前更新展開
***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 3天前更新展開
Role Summary: The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. Job Responsibility: －Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications. －Establish qualification requirements for new technology and product introduction. －Perform rigorous statistical analysis of reliability characterization data. －Enable high reliability during volume production by working with product groups to address risk areas. －Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. －Communicate study conclusions and recommendations to internal and external teams. Job Qualification: －Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. －Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). －Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. －Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM. －Must be curious, proactive, and detail-oriented. －Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 高雄市楠梓區 3年工作經驗 3天前更新展開
Job Responsibilities - To be the owner for manufacturing test on the released products. - Responsible for test program introduce to mass production - Responsible for NPI (after R-gate released) test data analysis and feedback to BL/PETE if any improvement needed - To be the owner for duplicated test hardware by performing debug and qualification, MSC (Gage R&R) analysis and release report - Responsible for 1st line hold lot disposition, including low yield, QA fail .......etc - To initial and work with related process owners on testing processes, documentation, and best practices - Participate in or drive test automation initiatives when applicable Required Qualifications - 3+ years of experience as a Test Engineer - Solid understanding of software/system testing methodologies - Familiarity with Linux environments and command-line operations - Experience with machine language (e.g., Java, C++) - Experience in system, embedded, hardware, or manufacturing testing - Strong analytical and problem-solving skills - Strong sense of ownership and responsibility for product quality English communication, reading, writing
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 高雄市楠梓區 工作經歷不拘 3天前更新展開
Job Description - Main contact window with business lines (BLs) to deliver a high quality and manufacturable product for IC test production, meeting or exceeding the required time to market or product cost. - Take lead of new product introduction (NPI) for IC test - To coordinate with related BLs (business line) and align with wafer/final test factories to prepare the product transfer - To improve new product introduction procedure to enable smooth product transfer - To reduce risk and impact to customers and factories, escalation management, e.g. reduce risk and impact by right and timely escalation - To ensure no gap on test tooling availability Facilitate IC test data review and process for planning forecast, take responsibility on test technical data (and improvement plan) in time and accuracy - To follow up test improvement projects, hold lots, progress of New Product Introduction, test buy off…etc. - Process of Test Engineering Notice and Enovia ECO Requirement - Bachelor degree (or above), Engineering background is preferred. - Excellent communication skills (English/Mandarin, TOEIC＞600) - Good logic thinking - Be familiar with MS Office tool - 1 yrs experience in IC testing or related working experience is preferred
分紅入股年終獎金三節獎金激勵獎金員工團保 -
