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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
1. SoC system power/performance analysis and improve 2. Develop IP power model for use cases (simulation and measurement for correlation) 3. Co-work with IP team to optimize power model (power reduction and power correctness) 4. Power analysis in SOC architecture, use cases and IP design (power/performance/area) 5. Planning low power architecture and power management
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
Challenge is the essences of opportunity. Challenge breakthrough creates innovations. In here, you are encouraged to embrace challenge, bring your ideas into product, create the vision into reality. You will need to design and evaluate next-generation NOC architecture, fulfilling cutting-edge product features and demands, meeting the performance/power/cost/schedule target, with the passion of coordination among matrix management teams.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
In this role, you will be a member of the System-on-Chip (SoC) Infrastructure team, responsible for Architecture and design for high-performance, low-power on chip interconnect and fabric components. Analyze the interconnect fabric at SOC level and sub-subsystem level and configure fabric components to meet bandwidth, latency, power needs of SOC. Work with cross function teams (architect, hardware, software, verification…) to develop system models and IPs for different architectural options for power, performance and cost trade offs.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
In this role, you will be a member of the System-Level-Cache (SLC) design team, working with architecture, modeling, silicon, software and other design teams to develop competitive SLC design. We are looking for highly motivated, hands-on individuals who are passionate about memory performance improvement to benefit memory access behavior in sophisticated system. Major Responsibilities: •Co-work with system architect to develop competitive memory system architecture • Analyze/improve memory system performance including latency and efficiency • Responsible for micro architecture planning and RTL design coding •Integrate IP into project and meet schedule and P.P.A. requirement •Co-work with DV team to well verify RTL design •Support software team to resolve memory system related issue
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
In this role, you will be responsible to develop new hardware/chip architectures, technologies, designs and methodologies for Mediatek’s silicon solution to address advanced chiplet architectures in 2D, 2.5D and 3D configurations. Mediatek provides the challenging and exciting technical position where you will have the opportunities to explore and define the next generation silicon solutions. Major Responsibilities: • Develop new product and chip architectures, analyze the key metrics such as power, performance, area, scalability and reusability for chiplet • Develop new methodologies for chiplet design and mass production flow
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 315天前更新展開
- Develop robust 3DIC PDN considering PDN impacts - Build and analyze 3DIC IR results and propose solutions - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches - Explore EDA tool new features and introduce to project team
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 315天前更新展開
1 Develop the IR signoff criterion for leading process node and 3DIC. 2 Maintain the IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable IR violation 3 Develop new IR signoff methodology to be applied during chip synthesis/APR/STA/IR . 4 SPICE correlation for new IR signoff criterion 5 Regression test for every signoff methodology by IR results
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 315天前更新展開
1. 10G/5G/2.5G Ethernet MAC/ BASET PHY開發 2. 訊號處理與通訊演算法實現 3. 系統整合與驗證
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 315天前更新展開
IO電路和ESD防護設計, 工作內容包含 (1) ESD/LUP防護設計 (2) IC ESD/LUP防護檢查 (3) 有EOS/Surge/System ESD 設計經驗尤佳
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 315天前更新展開
• 帶領與整合類比IP團隊與技術, 開發新的SOC或ASIC產品 • You will work as part of analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet product schedules. • Multi-task skills will be key to lead several tasks of project at a time. • Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application. • Convert data into a clear story to communicate to partners and organizations at all levels. • Pull together regular project status presentations for executive leadership review. • Identify risks, develop mitigation strategies and facilitate conflict resolution. • Collaborate with software/hardware teams for silicon validation of analog IPs • Deliver highly focused and detailed issue reporting, bug tracking and communication of risks and status
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