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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 269天前更新展開
1. 802.11 無線網路驅動程式與韌體開發. 2. 802.11 無線網路客制化協議開發. 3. 802.11 無線網路驅動程式與相關軟件在嵌入式系統的整合 4. 802.11 無線網路模塊驗證. 5. 重要客戶支持及專案管理.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 269天前更新展開
1. 無線通訊系統安全開發 2. 無線通訊系統驅動程式開發 3. 無線通訊系統軟體穩定性 4. 無線通訊晶片驗證 5. 熟悉Linux/RTOS 核心
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 269天前更新展開
1. Wi-Fi 驅動程式/韌體開發設計及驗證 2. Wi-Fi 等無線晶片之跨層架構介面設計 3. 協助研發軟體新技術與新工具 4. 產品量產問題分析與解決 5. 無線網路(802.11) 演算法和系統效能探索 6. 無線網路新規格前期定義，架構設計及軟硬體分工
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 4年工作經驗 269天前更新展開
(1) 負責WLAN網路架構系統評估 (2) 負責Wi-Fi7 新功能開發與軟硬體架構規劃 (3) 負責新規格 Wi-Fi7 無線網路系統軟硬體雛型系統開發, 模擬與系統效能分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 269天前更新展開
1.發展多模NR/LTE L1/DSP軟體, 包含:狀態機/通道排程/數據機及RF控制 2.在嵌入式系統實現OFM信號處理機制 3.熟悉ASIP/DSP架構下的數位通訊
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
1. SoC physical design technology & methodology development for optimal PPA, including floorplan, design planning, DFT, clock planning, place & route, and timing closure 2. Support key technology or methodology landing to real projects. Perform floorplan, DFT, clock planning, place and route, timing closure, ECO, IR signoff 3. Manage schedule, resolve design and flow issues, drive methodologies and execution
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
1. Perform pre-silicon analysis to recommend sensor usage for adaptive voltage scaling 2. Perform post-silicon correlation and modeling related to adaptive voltage scaling 3. Develop and improve circuits and methodologies related to adaptive voltage scaling
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
1. SoC system power/performance analysis and improve 2. Develop IP power model for use cases (simulation and measurement for correlation) 3. Co-work with IP team to optimize power model (power reduction and power correctness) 4. Power analysis in SOC architecture, use cases and IP design (power/performance/area) 5. Planning low power architecture and power management
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
Challenge is the essences of opportunity. Challenge breakthrough creates innovations. In here, you are encouraged to embrace challenge, bring your ideas into product, create the vision into reality. You will need to design and evaluate next-generation NOC architecture, fulfilling cutting-edge product features and demands, meeting the performance/power/cost/schedule target, with the passion of coordination among matrix management teams.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
In this role, you will be a member of the System-on-Chip (SoC) Infrastructure team, responsible for Architecture and design for high-performance, low-power on chip interconnect and fabric components. Analyze the interconnect fabric at SOC level and sub-subsystem level and configure fabric components to meet bandwidth, latency, power needs of SOC. Work with cross function teams (architect, hardware, software, verification…) to develop system models and IPs for different architectural options for power, performance and cost trade offs.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
In this role, you will be a member of the System-Level-Cache (SLC) design team, working with architecture, modeling, silicon, software and other design teams to develop competitive SLC design. We are looking for highly motivated, hands-on individuals who are passionate about memory performance improvement to benefit memory access behavior in sophisticated system. Major Responsibilities: •Co-work with system architect to develop competitive memory system architecture • Analyze/improve memory system performance including latency and efficiency • Responsible for micro architecture planning and RTL design coding •Integrate IP into project and meet schedule and P.P.A. requirement •Co-work with DV team to well verify RTL design •Support software team to resolve memory system related issue
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