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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
In this role, you will be responsible to develop new hardware/chip architectures, technologies, designs and methodologies for Mediatek’s silicon solution to address advanced chiplet architectures in 2D, 2.5D and 3D configurations. Mediatek provides the challenging and exciting technical position where you will have the opportunities to explore and define the next generation silicon solutions. Major Responsibilities: • Develop new product and chip architectures, analyze the key metrics such as power, performance, area, scalability and reusability for chiplet • Develop new methodologies for chiplet design and mass production flow
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 269天前更新展開
- Develop robust 3DIC PDN considering PDN impacts - Build and analyze 3DIC IR results and propose solutions - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches - Explore EDA tool new features and introduce to project team
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 269天前更新展開
1 Develop the IR signoff criterion for leading process node and 3DIC. 2 Maintain the IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable IR violation 3 Develop new IR signoff methodology to be applied during chip synthesis/APR/STA/IR . 4 SPICE correlation for new IR signoff criterion 5 Regression test for every signoff methodology by IR results
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 269天前更新展開
1. 10G/5G/2.5G Ethernet MAC/ BASET PHY開發 2. 訊號處理與通訊演算法實現 3. 系統整合與驗證
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 269天前更新展開
IO電路和ESD防護設計, 工作內容包含 (1) ESD/LUP防護設計 (2) IC ESD/LUP防護檢查 (3) 有EOS/Surge/System ESD 設計經驗尤佳
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
• 帶領與整合類比IP團隊與技術, 開發新的SOC或ASIC產品 • You will work as part of analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet product schedules. • Multi-task skills will be key to lead several tasks of project at a time. • Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application. • Convert data into a clear story to communicate to partners and organizations at all levels. • Pull together regular project status presentations for executive leadership review. • Identify risks, develop mitigation strategies and facilitate conflict resolution. • Collaborate with software/hardware teams for silicon validation of analog IPs • Deliver highly focused and detailed issue reporting, bug tracking and communication of risks and status
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 269天前更新展開
1. 5G NR/Pre6G 通訊平台開發 (a) 5G gNodeB/UE 測試系統 開發 (b) L1 test mode演算法通訊平台開發 2. 5G NR通訊系統分析 (a) 5G NR實體層規格及流程驗證 (b) 基頻演算法設計驗證及訊號分析 (c) 整體系統效能驗證與流程分析 3. Modem 4/5G system level / physical layer issue analysis (a) Develop and integrate build and auto testing process (b) Collect / analyze system requirement & system design (c) Support urgent system function or performance problem
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 269天前更新展開
根據不同專案使用的各種CPU架構: 1. 計畫用於system bring-up, DVT, 以及量產所需的function pattern 2. 開發function pattern(程式撰寫與模擬等等) 3. 基於對CPU design的了解以及pattern調整, debug post-silicon問題(DPPM fail or RMA等等)
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 269天前更新展開
The Modem Technology Architecture team is currently involved in the architecture definition, design and validation of MediaTek’s 5G NR chipsets. In your role as Modem Architect, you will be responsible for the architecture definition of state of the art cellular modems used in User Equipment (UE) devices. You will be comfortable working across HW/SW boundaries and will have experience exploring and quantifying the impact of different architecture decisions on performance, area and power consumption.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 269天前更新展開
1. 研究IP開發測試計畫, 環境, 驗證與除錯. 2. IP開發驗證. 3. 研究分析IP比較與效能評比. 4. 制定IP驗證機制與強化重複性測試環境以提供給產品使用. 5. 負責在計畫時程規劃內完成IP驗證與除錯.
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