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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 台北市松山區 5年工作經驗 1天前更新展開
1.負責SAP系統至少1模組之日常維運、需求實現、解決痛點、效能監控及調校，確保後勤單位在使用系統上能正常運作，甚而優化流程、增加效率、加強稽核。 2.跨系統資料整合，確保SAP RFC、BAPI與協作系統interface日常維運、需求實現、解決痛點、效能監控及調校，甚而優化流程、增加效率、加強稽核。
安胎假家庭照顧假全勤獎金年節獎金年終獎金 - 月薪40000元 台中市南屯區 2年工作經驗 1天前更新展開
1.電腦基本硬體維修及問題排除 2.資訊資產盤點、管理與設備維護 3.網路系統維護與異常排除 4.伺服器基礎管理與權限管控 5.資訊設備產品採購作業 6. 新進同仁設備設定 7. 協助資料庫系統管理及備援
績效獎金員工團保員工公出特別保險伙食津貼尾牙 - 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 41天前更新展開
職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 41天前更新展開
職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 41天前更新展開
職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 41天前更新展開
職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 今天剛更新展開
1.數位轉型推動－專案統籌、策劃、並推動數位轉型。 2.建立完善的數據基礎，建立營運管理指標並進行分析改善。並協助其他部門進行業務改善。 3.專案管理：負責規劃和執行數位轉型專案，包括設定目標、制定計畫和監控執行進度。 4.其他主管交辦事項。 ※該職務會需要與本社進行業務的溝通，故日文程度有JLPT N2以上要求。
需穿著員工制服員工在職教育訓練良好升遷制度全勤獎金年節獎金 - 面議（經常性薪資達4萬元或以上） 高雄市左營區 工作經歷不拘 41天前更新展開
職責要求 1.辦理電力系統相關工程技術，需熟悉電驛保護協調、電力相關標準，並執行型態管理，以確保設備設計功能正常、維持營運安全。 2.協辦電力系統升級、置換等相關工程之技術研擬及現場管理作業，包含招標及技術文件撰稿、現勘、監工、測試、點移交作業等。 3.系統性設備異常營運與維修技術支援，需與採購、設備介面單位及契約承商等協作，執行專案工程履約管理作業，確保工程契約符合安全準則。 4.協助評量施工與測試作業風險，規範風險減輕需求。 5.分責承辦部門工程合約之設計審查、意見彙整與澄清、介面與排程協調、施工與測試監察進度管控與彙報等合約執行作業項目。 6.依公司政策，辦理與其他機關單位之技術協助與相關業務。 任職資格 1.大學以上，電機電子工程相關系所，英文中上可溝通及閱讀英文文件 2.具高考電機工程技師尤佳 3.熟悉工程專案管理作業與一般採購合約流程與管理 4.熟悉軌道供電系統相關子系統包括：變電系統、輸電系統、電力監控系統、配電系統及道旁機電系統等
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 月薪45000元 台中市大雅區 工作經歷不拘 3天前更新展開
1. 半導體生產設備安裝、故障排除、維護、了解並解決客戶問題。 2. 當需要日本方面協助時，能準確傳達資訊給日本，並理解日本的回饋，進而執行問題改善。 3.需於無塵室工作 4.其他主管交辦事項 5.須配合出差及加班(合法給付加班費) 所需技能： 1. 設備FSE現地客服工程師經驗（若曾對應半導體大廠經驗者優先） 2. 日語能力（N2以上）能流利與日本人對談
就業保險產假產檢假安胎假家庭照顧假 - 月薪45000~57000元 新北市泰山區 1年工作經驗 8天前更新展開
1. 封測工程批於外包廠所需產能與進度之協調 2. NTC Consign 外包廠之設備與Tooling 交貨進度規劃與跟催 3.外包廠季評核進度規劃、評分與報告 4. RDL 外包廠索賠案件之處理 5. 客戶對外包廠資料需求協助跟催 ( RBA、碳足跡、BCP等)
員工電影國內旅遊員工聚餐尾牙家庭日 - 面議（經常性薪資達4萬元或以上） 新北市土城區 工作經歷不拘 今天剛更新展開
1.精密零件的模具設計 ( 衛星通訊, 光學元件, 光通訊 等產業相關零部件 ) 2.超精密加工 3.各製造工段 ( CNC, EDM, WEDM, UPM…等 ) 協同製程改善及優化 4.撰寫可製造性評估 ( DFM ) 5.模流分析報告撰寫與導入新工程塑料分析 ( CAE ) 6.協同量產單位 ( Injection ) 分析成型不良解析及穩定性提升
- 月薪38000元 桃園市桃園區 工作經歷不拘 8天前更新展開
1. 負責SMT 及 PCA 段生產設備操作保養，依分發單位為主。 SMT 段：印刷機、置件機、REFLOW。 PCA 段：波峰焊、選擇焊、分板機、壓接機、點(噴)膠機。 2. 產品良率優化改善，設備改善。 3. 新進同仁教育訓練及SOP撰寫。 4. 同仁工作事項安排及KPI制訂執行。
員工及眷屬喪葬補助社團補助員工在職教育訓練年節獎金員工生日禮金 - 面議（經常性薪資達4萬元或以上） 高雄市大寮區 3年工作經驗 今天剛更新展開
1. MES 系統架構完善及程式優化 (SA, SD)，功能開發與效能調校 2. 協同跨系統整合與數據應用：ERP、MES、WMS 等核心系統的串接，並透過數據分析（如生產履歷、效率追溯）持續優化產線 3. 智能工廠 SOP 與操作準則的制定規劃與推行，確保現有廠區高效且規範化運作 4. MES日常維運、異常排除
- 月薪52000元 新北市土城區 2年工作經驗 今天剛更新展開
1.負責NB安規能耗前期設計與評審，確保産品符合安規能耗法規要求，降低Safety&Energy風險； 2.負責NB安規能耗測試，制定測試計劃； 3.執行Safety&Energy認證，確保產品如期取證； 4.各階段協助安規能耗相關問題點分析，提供有效的整改方案
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