面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘 1天前更新
【About the Role】
Join our cutting-edge team to shape the future of communication technologies.
As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems.
Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems.
Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards.
With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing.
This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments.
【Key Responsibilities】
1. Develop state-of-the-art baseband algorithms to enhance communication system performance.
2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability.
3. Lead communication system verification efforts to ensure system integrity and performance.
4. Innovate in architecture and algorithm design for low-power, high-speed communication systems.
5. Apply digital signal processing techniques to optimize mixed-signal system functionality.
6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards.
7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
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