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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 彰化縣彰化市 工作經歷不拘 4天前更新展開
1.銷售公司提供之商品（免自行準備貨源） 2.對銷售工作有熱忱，喜歡與人互動 3.積極負責，具備團隊合作精神 4.需具備駕照，自備車輛佳 收入依能力與出勤率計算 多出勤、多努力 ＝ 多收入 *投履歷合適者會撥打電話聯繫面試時間*
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 107天前更新展開
1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 2. 系統應用詳細電源需求與控制架構之分析與優化 3. 電源管理芯片規格制定與新技術之開發.
- 面議（經常性薪資達4萬元或以上） 台中市西屯區 工作經歷不拘 4天前更新展開
【BEART 招募銷售夥伴｜高獎金、高成長】 你不是在找工作， 你是在找一個能讓收入翻倍的機會。 BEART 專注生活選品 / 香氛 / 美容工具市場， 市場接受度高、回購率穩定。 我們正在找： ✔ 想拚收入的人 ✔ 有企圖心的人 ✔ 願意挑戰高獎金的人 ✔ 想從銷售做到帶團隊的人 我們提供： ✓ 高抽成制度 ✓ 完整銷售培訓 ✓ 熱門商品資源 ✓ 晉升主管 / 經銷機會 ✓ 能力越強，收入無上限 不是領死薪水， 而是靠能力決定收入。 想賺3萬是工作；想賺10萬以上，是選擇。 加入 BEART，和會賺錢的人一起成長。 需自備小型車以上車輛
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 時薪196元 台北市大安區 工作經歷不拘 16天前更新展開
Do you want to be part of a smart and passionate team of researchers, advancing artificial intelligence to the next level of end-user experience in their daily lives? MediaTek is seeking driven and brilliant young students to join our efforts by providing Internship placements. We are currently working to expand the frontiers of Deep Learning frameworks for Computer Vision and Natural Language Processing and we hope you can join us! The ideal candidate is open-minded, passionate about learning theory, and looks forward to both practical and challenging problems. • You will be working towards or recently have completed a PhD in a quantitative field such as Computer Science, Mathematics, Physics or Engineering. • You have a good knowledge of the foundations of Deep Learning and Neural Networks, including some experience with Machine Learning frameworks (Tensorflow, PyTorch, JAX) • You are a proficient scientific communicator. You are committed to your goals and working in a team. • You are eager to tackle the state of the art problems in the field. We want your ideas to shine! As a Deep Learning Researcher in our team, you will collaborate with our Researchers and with worldwide colleagues, stay up and above the state of the art, initiate with novel ideas, and develop them into algorithms and applications that make the real difference in everyday devices. You will also push your contribution by publishing at top-tier conferences, such as NeurIPS, ICML, ICLR, CVPR, ACL, ICRA, ACM.
- 月薪29500~50000元 新竹市東區 3年工作經驗 16天前更新展開
開發模擬以及PoC測試平台, 工作包括 - 實作分散式運算架構 - 利用Kubernetes container 管理架構 - 實作概念性驗證
- 月薪35000~37000元 桃園市中壢區 1年工作經驗 2天前更新展開
餐廳出納員1 薪資35000元 全勤2000元 1. 負責結帳、收銀之工作，具備收銀能力，熟悉結帳流程並處理顧客支付事宜 2. 熟悉操作POS機、收銀機、刷卡機 3. 協助接聽來店電話、回覆客人相關問題 4. 對餐飲服務工作有熱忱 5. 個性積極主動、有責任感、抗壓性佳 歡迎加入我們的團隊，與我們一同為顧客提供愉快的用餐體驗！立即投遞履歷，期待您的加入！
員工生日禮金年終獎金三節獎金員工聚餐需穿著員工制服 - 面議（經常性薪資達4萬元或以上） 新北市中和區 3年工作經驗 1天前更新展開
1. 會計帳務紀錄 2. 發票開立、對帳與報稅作業 3. 協助編製各項財務報表及憑證整理 4. 協助年度結帳、查帳及稅務申報 5. 主管交辦事項
就業保險產假產檢假員工生日禮金年終獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 107天前更新展開
1. 系統應用電源需求與控制架構分析 2. 電源管理晶片規格制定與驗證 3. 類比電路開發與驗證 4. 驗證電路板設計 5. 自動化測試開發
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 16天前更新展開
1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 16天前更新展開
• Work with the architecture/micro-architecture/design teams to do white box testing. • Create testplans based on the micro-architecture document with the design team. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Build custom BFMs for co-sim based module level verification. • Add assertions and checkers to facilitate verification. • Work with the design team to do module level formal verification. • Create controlled random testcases. Pre-debug and provide debug reports. • Check functional coverage and code coverage.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 16天前更新展開
• Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 16天前更新展開
Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 16天前更新展開
Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 45天前更新展開
參與先進製程下ASIC及其他產品的開發與導入。 支援新產品線，如CPO、IVR、cHBM......等技術的設計、驗證與量產導入。 與跨部門團隊合作，解決產品開發過程中的技術問題，確保專案順利執行。 持續追蹤先進半導體製程與新穎封裝技術的產業動態，提供技術建議。
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