面議（經常性薪資4萬/月含以上） 台南市善化區 5年工作經驗 3天前更新
1. Familiarity with Verilog/VHDL RTL coding and FPGA/CPLD design process is must.
2. Experienced in Altera/Xilinx/Lattice FPGA/CPLD and development/simulation tools.
3. Cooperated with HW/SW/FW teams to perform FPGA/CPLD design bring-up, debug, validation and maintenance.
4. Documented for the design specification, test plan and development issue history.
5. Knowledge in the various interface protocol such as I2C/SPI/LPC/UART/PCIe/DDR.
6. Understanding in the high speed design architecture and optimized the timing performance.
7. Implemented the new technology, algorithm and design concept in CPLD/FPGA
8. Experience for RTL synthesis、coding & simulation is plus.
9. Responsible for ASIC constraint validation with ASIC Vendor、coordinate project from end to end.
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