面議(經常性薪資達4萬元或以上) 新竹市東區 4年工作經驗 3天前更新
1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform.
2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan.
3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.
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