- 面議（經常性薪資達4萬元或以上） 台中市西屯區 工作經歷不拘 1天前更新展開
1.銷售公司提供之商品（免自行準備貨源） 2.對銷售工作有熱忱，喜歡與人互動 3.積極負責，具備團隊合作精神 4.需具備駕照，自備車輛佳 收入依能力與出勤率計算 多出勤、多努力 ＝ 多收入 *投履歷合適者會撥打電話聯繫面試時間*
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 月薪40000~50000元 新北市新店區 2年工作經驗 2天前更新展開
1. 國內網路系統整合業務，負責開發潛在客戶與開拓市場，以達成業績目標。 2. 定期拜訪經銷客戶，維繫穩定客戶關係。 3. 負責產品報價及產品展示，並處理帳款回收相關事宜。 4. 進行商品行銷，產品特色分析介紹，並提供產品購買的建議。 5. 具有資訊安全及網路整合領域銷售經驗者佳。
員工在職教育訓練良好升遷制度產假產檢假 - 月薪40000~50000元 台中市北區 2年工作經驗 2天前更新展開
1. 國內網路系統整合業務，負責開發潛在客戶與開拓市場，以達成業績目標。 2. 定期拜訪經銷客戶，維繫穩定客戶關係。 3. 負責產品報價及產品展示，並處理帳款回收相關事宜。 4. 進行商品行銷，產品特色分析介紹，並提供產品購買的建議。 5. 具有資訊安全及網路整合領域銷售經驗者佳。
員工在職教育訓練良好升遷制度產假產檢假 - 面議（經常性薪資達4萬元或以上） 新北市中和區 3年工作經驗 2天前更新展開
1. 會計帳務紀錄 2. 發票開立、對帳與報稅作業 3. 協助編製各項財務報表及憑證整理 4. 協助年度結帳、查帳及稅務申報 5. 主管交辦事項
就業保險產假產檢假員工生日禮金年終獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 19天前更新展開
1. 系統應用電源需求與控制架構分析 2. 電源管理晶片規格制定與驗證 3. 類比電路開發與驗證 4. 驗證電路板設計 5. 自動化測試開發
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 19天前更新展開
• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 19天前更新展開
1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 19天前更新展開
• Work with the architecture/micro-architecture/design teams to do white box testing. • Create testplans based on the micro-architecture document with the design team. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Build custom BFMs for co-sim based module level verification. • Add assertions and checkers to facilitate verification. • Work with the design team to do module level formal verification. • Create controlled random testcases. Pre-debug and provide debug reports. • Check functional coverage and code coverage.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 19天前更新展開
• Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 19天前更新展開
• Work with the architecture team in the early stage of the project to derive various architecture and micro-architecture proposals. • Work with the performance architect to create performance models for various functional blocks of a microprocessor, memory subsystem and the whole core. • Work with design teams to analyze performance corner cases and provide feedback to the architecture team.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 19天前更新展開
Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 19天前更新展開
Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
-
