面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘 1天前更新
工作項目:
Verification for High Speed PHY projects, which includes:
1. Responsibility for test plans, testbench documentation and implementation.
2. Use SystemVerilog language, SVA and UVM methodology for block level verification.
3. Debug tests with design engineers to deliver functionally correct design blocks.
4. Close coverage measures to identify verification holes and show progress towards tape-out.
5. Write scripts to automate routine parts of verification workflow.
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