- 時薪240~300元 桃園市觀音區 工作經歷不拘 11天前更新展開
蝦皮~寶倉街堆高機手 作業時段 早班 09:00~18:00 晚班 16:00~01:00 大夜班 22:00~07:00 (短)22:00~02:00 蝦皮~寶倉街理貨撿貨 作業時段 早班 07:00~16:00 早班 08:00~17:00 早班 09:00~18:00 晚班 16:00~01:00 大夜班 22:00~07:00 (短)22:00~02:00 長期 排休制 薪資依照檔期加碼各有不同 ※勞健保、勞退6％、公司制服 【應徵方式】週一至週五 09:00-21:00 可連絡 游專員加LINE好友優先回復 電聯 0928-620-987 Line ID: 0928-620-987
禮品全勤獎金三節獎金績效獎金意外險 - 時薪280~300元 桃園市楊梅區 工作經歷不拘 11天前更新展開
⭐️高時薪 280 ⭐️吃飯時間1H ⭐️有堆高機證照 另有獎金 地點:楊梅區梅獅路 ►工作內容 : 包裹理貨、分類、包裝理貨 ►休假方式 : 排休8天 ►休息時間 : 上下午各15分鐘 中餐間休1小時 ►提供勞健保、額外津貼、達標獎金 ►⏰工作時間 : ❣️《大夜班》24:00-09:00 可日領 可日領 可日領 應徵方式 ✉LINE ID:0928-620-987 ☎加入後方便留下姓名/電話/截圖職缺
禮品全勤獎金三節獎金績效獎金意外險 - 時薪280~300元 桃園市楊梅區 工作經歷不拘 11天前更新展開
⭐️高時薪 280 ⭐️吃飯時間1H ⭐️有堆高機證照 另有獎金 地點:楊梅區梅獅路 ►工作內容 : 包裹理貨、分類、包裝理貨 ►休假方式 : 排休8天 ►休息時間 : 上下午各15分鐘 中餐間休1小時 ►提供勞健保、額外津貼、達標獎金 ►⏰工作時間 : ❣️《大夜班》24:00-09:00 可日領 可日領 可日領 應徵方式 ✉LINE ID:0928-620-987 ☎加入後方便留下姓名/電話/截圖職缺
禮品全勤獎金三節獎金績效獎金意外險 - 時薪280~300元 桃園市楊梅區 工作經歷不拘 11天前更新展開
⭐️高時薪 280 ⭐️吃飯時間1H ⭐️有堆高機證照 另有獎金 地點:楊梅區梅獅路 ►工作內容 : 包裹理貨、分類、包裝理貨 ►休假方式 : 排休8天 ►休息時間 : 上下午各15分鐘 中餐間休1小時 ►提供勞健保、額外津貼、達標獎金 ►⏰工作時間 : ❣️《大夜班》24:00-09:00 可日領 可日領 可日領 應徵方式 ✉LINE ID:0928-620-987 ☎加入後方便留下姓名/電話/截圖職缺
禮品全勤獎金三節獎金績效獎金意外險 - 時薪240~320元 桃園市大園區 工作經歷不拘 11天前更新展開
▃▃▃▼ 重點整理介紹 ▼▃▃▃ ►工作地點 : 近大園市區 ►工作內容 : 衣服分類、出貨、包裝 ►休假方式 : 可自行排休8天 ▃▃▃▼ 上班時段可任選 ▼▃▃▃ ►上班時間 : (固定班) 【日班】- 09:00-18:00 (8H) 檔期高薪6/17~6/22 時薪240起 【日班】- 08:00-20:00 (8H) ▃▃▃▼ 班別薪資 ▼▃▃▃ 【日班】時薪210$ 【日班檔期】時薪240$ ♡加班320起 ▂▂▂【享有福利】▂▂▂ ❥環境優良 人緣好相處 歡迎大家一起當同事 ❥享勞保、健保、團保、勞退6％ ▃▃▃▼ 應徵方式看這邊 ▼▃▃▃ ✉LINE ID:@213ttamd 電話:0916-717-693 李專員
禮品全勤獎金三節獎金績效獎金意外險 - 時薪300~305元 桃園市楊梅區 工作經歷不拘 11天前更新展開
⚡可日領 週領 領薪快速方便⚡ ⭐️高時薪300$-305$ ⭐️月入6萬不是問題 ⭐️免費交通車 ⭐️吃飯時間1H ⭐️提供私人置物櫃 ⭐️享有加班費另計 ⚡每週額外津貼加給 不定時加碼⚡ ▃▃▃▼ 重點整理介紹 ▼▃▃▃ ►工作地點 : ✅楊梅和平路 ►工作內容 : 包裹理貨、分類、包裝理貨 ►休假方式 : 排休8天 ►休息時間 : 上下午各15分鐘 中餐間休1小時 ►提供勞健保、額外津貼、達標獎金 ▃▃▃▼ 上班時段 薪資計算 ▼▃▃▃ ►⏰工作時間 : ❣️ 【晚班】-24:00-09:00 時薪300$-305$ ▃▃▃▼ 應徵方式看這邊 ▼▃▃▃ ♡────────────♡ ✉LINE ID@213ttamd ☎可撥0916-717-693李專員 ☎加入後方便留下姓名/電話/截圖職缺 ♡────────────♡
禮品全勤獎金三節獎金績效獎金意外險 - 時薪240~320元 桃園市大園區 工作經歷不拘 11天前更新展開
▃▃▃▼ 重點整理介紹 ▼▃▃▃ ►工作地點 : 近大園市區 ►工作內容 : 衣服分類、出貨、包裝 ►休假方式 : 可自行排休8天 ▃▃▃▼ 上班時段可任選 ▼▃▃▃ ►上班時間 : (固定班) 【日班】- 09:00-18:00 (8H) 檔期高薪6/17~6/22 時薪240起 【日班】- 08:00-20:00 (8H) ▃▃▃▼ 班別薪資 ▼▃▃▃ 【日班】時薪210$ 【日班檔期】時薪240$ ♡加班320起 ▂▂▂【享有福利】▂▂▂ ❥環境優良 人緣好相處 歡迎大家一起當同事 ❥享勞保、健保、團保、勞退6％ ▃▃▃▼ 應徵方式看這邊 ▼▃▃▃ ✉LINE ID:@213ttamd 電話:0916-717-693 李專員
禮品全勤獎金三節獎金績效獎金意外險 - 時薪230~230元 桃園市大園區 工作經歷不拘 11天前更新展開
誠徵臨時人員 早班時段 08:00-20:00 (檔期) 早班 07:00-15:00 中班 15:00-23:00 夜班 23:00-07:00 以上薪資 皆230起 應徵方式 Line 0928620987
禮品全勤獎金三節獎金績效獎金意外險 - 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 52天前更新展開
職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 52天前更新展開
職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 52天前更新展開
職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 52天前更新展開
職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 高雄市左營區 工作經歷不拘 52天前更新展開
職責要求 1.辦理電力系統相關工程技術，需熟悉電驛保護協調、電力相關標準，並執行型態管理，以確保設備設計功能正常、維持營運安全。 2.協辦電力系統升級、置換等相關工程之技術研擬及現場管理作業，包含招標及技術文件撰稿、現勘、監工、測試、點移交作業等。 3.系統性設備異常營運與維修技術支援，需與採購、設備介面單位及契約承商等協作，執行專案工程履約管理作業，確保工程契約符合安全準則。 4.協助評量施工與測試作業風險，規範風險減輕需求。 5.分責承辦部門工程合約之設計審查、意見彙整與澄清、介面與排程協調、施工與測試監察進度管控與彙報等合約執行作業項目。 6.依公司政策，辦理與其他機關單位之技術協助與相關業務。 任職資格 1.大學以上，電機電子工程相關系所，英文中上可溝通及閱讀英文文件 2.具高考電機工程技師尤佳 3.熟悉工程專案管理作業與一般採購合約流程與管理 4.熟悉軌道供電系統相關子系統包括：變電系統、輸電系統、電力監控系統、配電系統及道旁機電系統等
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 時薪216元 台中市霧峰區 工作經歷不拘 2天前更新展開
工作內容： 1. 負責為客戶車輛加油服務，熟悉汽油與柴油加注流程，確保操作安全與準確。 2. 處理收銀服務，進行現金與信用卡交易結算，保障交易準確性。 3. 協助介紹站內產品與促銷活動，提供建議並協助顧客兌換贈品。 4. 維持加油站區域的整潔與秩序，包括垃圾處理及基礎清潔工作。 5. 確保營業結束後帳務正確，進行會計出納對帳與報表製作。 6. 協助站內庫存管理，如油品、贈品及週邊商品的定期補充與盤點。 7. 遵守公司安全規範，必要時參加緊急應變模擬演練，確保自身及顧客安全。 我們期待與擁有熱誠及責任感的你，一起為客戶提供優質的加油站服務！
意外險員工團保產假勞退提繳金職災保險 -
