面議(經常性薪資達4萬元或以上) 新竹縣竹北市 工作經歷不拘 144天前
AS deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow.
-SHBG DV is in charge of development and implementation of TV, monitor and smart home product line verification plan.
-It included: integrated simulation/verification env development, BUS fabric verification, Serdes IP verification, and architecture explore by ESL.
-Need to leverage the latest EDA tool and concept to accomplish the verification plan
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