面議（經常性薪資達4萬元或以上） 台南市新市區 工作經歷不拘 3天前更新
職務說明：
1. Create formal verification test plan.
2. Develop formal verification environment.
3. Run formal verification and regression, debug failures and analyze coverage.
4. Support other members in deploying formal verification.
5. Survey new formal applications and develop related workflow.
6. Enhance and maintain formal verification workflow.
徵才條件：
A. Key qualifications :
1. Master‘s or above in Electrical Engineering, Computer Science.
2. Familiar with standard verification concepts and workflow.
3. Familiar with SystemVerilog and Verilog.
4. Familiar with scripting languages (Perl, Python, etc.).
5. Good communication skills.
B. Preferred qualifications :
1. Familiar with SystemVerilog Assertion (SVA).
2. Familiar with formal verification methodology.
3. Familiar with formal tools (JasperGold, VCFormal).
4. Practical experience in formal verification, able to apply strategies to resolve issues during the verification process.
5. Familiar with bus protocol concept (AMBA).
6. Familiar with UVM methodology.
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