面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 8年工作經驗 7天前更新
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https://careers.tsmc.com/careers/JobDetail?jobId=16346&source=1111
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.
We are looking for a technical manager who is excited to join a growing group of diverse talents responsible for driving novel memory solutions for the leading-edge AI and HPC chips. You will be part of a memory solution team developing high-density memory macro, complex analog, and chip interface circuits for advanced memory technology. We have crafted a team of outstanding engineers stretching around the globe. If you have the dream to develop new technologies and have the real impact on the future of AI compute, this is the ideal position for you.
Responsibilities:
1. Lead the designs of memory architecture, memory, analog and digital circuits, and test chip, ensuring they meet the performance, power, and area specifications.
2. Provide technical leadership in areas like memory read/write circuits, analog biasing circuits including LDO and charge pump, design-for-test (DFT), function verification, and memory chip integration.
3. Collaborate closely with technologists and customers to define PPA specifications, architecture, and design of memory circuits.
4. Demonstrate hands-on expertise in designing memory circuit blocks and utilizing EDA tools for timing, power, signal integrity, EM/IR analysis, static timing, and noise analysis.
5. Drive design verification and implement quality assurance methodologies for memory IP.
6. Define silicon test plans and provide support for post-silicon bring-up and debugging in collaboration with test teams.
7. Manage design projects by planning and organizing design resources, while addressing customer/client requests and events as they arise.
8. Work closely with cross-functional teams across global locations to ensure successful project execution.
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