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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 -建立並維護測試平台，進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果，協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板，支援系統驗證。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan. It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan Work location: Hsinchu/Taipei
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
[職缺內容] 1. 生成式 (Gen AI) 應用程式 for Camera Productivity Applica開發 (Win Form, Frontend) 2. 生成式 AI 技術 Survey 與 Landing [團隊簡介] 1.加入多媒體部門 (MM), 會專注核心相機軟體研發, 提供開放軟體架構給予不同產品線使用 2.重視軟體設計思維與軟件工匠團隊文化, 創造 Incredible In, Incredible Out 的相機應用軟件 3.落實 Solid 軟體開發流程,從軟件設計規範, 到執行 Code Review, Documentation 與 Auto Test 4.持續建置 Knowledge Base 與經驗傳承, Open Mind 持續導入創新而能提升生產力的 Methodology & Process 5.重視團隊 Partners 的 Career Path, Soft & Hard Skill Build p, 期待長期合作關係與相互成長 [加分項] 1.有前端 (Frontend) 與後端 (Backend) 的開發與佈署經驗, 不限語言與框架 2.有 Database 的 Scheme 設計與 Database 的使用經驗, 不限使用原生 SQL 或是 ORM (Object Relational Mapping) 3.有使用 RESTful API 進行程序整合的經驗 4.有 H5 與 Java Script 的開發經驗 5.有網路爬蟲 (Web Crawler) 經驗 [人選特質] 1.積極正面的態度: 期待人選能以正面的心態迎接工作中的挑戰, 並從中發掘成長與機會 2.終身學習精神: 在快速變化的科技領域, 持續學習是必要的, 期待人選對於新技術和知識有持續的熱情和追求 3.勇於面對挑戰: 面對困難或新領域時, 人選應具備勇氣和決心, 積極尋找並實施解決方案 4.邏輯思維能力: 清晰的邏輯思維對於軟體開發至關重要, 期待人選能夠系統性地分析問題, 並設計出合理且有效的解決方案 5.深思熟慮: 在決策時, 期待人選能深入考慮各種可能性和後果, 並能夠做出周全的決定, 考量的是整體解, 並非局部解法
- 月薪29500~48000元 新竹市東區 工作經歷不拘 27天前展開
(請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.
- 1111南台灣職場小語
【推薦給你】可週休二日(或固定休六日)、月薪３萬起工作機會！
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
1. 高速Serdes系統技術開發(200Gbps+), 包括電通訊與光通訊(optical interconnect) 2. 定義系統技術規格並與設計團隊(Analog, Digital, Algorithm)討論系統架構, 建立模型模擬評估 3. Serdes 關鍵技術評估與開發( e.g., Next Gen Serdes, optical nonlinearity compensation, CPO technology) 4. 協助Serdes IP驗證問題分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
• Design, simulate and test various building blocks for photonic ICs such as modulators, filters, and detectors. • Develop mathematical models of photonic components for co-simulation with electronic circuits. • Contribute to the integration and testing of Photonic & Electronic ICs, collaborate with cross functional teams to improve system performance and optimize designs. • Must be proficient in programming (e.g. Python or MATLAB) for design automation
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 27天前展開
1. 開發基於虛擬機的軟體平台和虛擬機管理技術。 2. 職責包括軟體功能和驅動程式的開發，以及硬體設計的整合。 3. 與其他軟體團隊、第三方和客戶的工程師進行合作。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前展開
1. Architecture design and RTL implementation for Smartphone and automotive chip 2. Smartphone SoC and mobile computing platform design. 3. System bus and high speed interface designs
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
1. Smartphone (Low Power Architect) and Automotive (Power control) 2. Not a management position 3. Short term:digital IP design/integration of power control IPs with zero bugs Long term:define power control arch for smartphone or automotive products develop new tech for power control
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 27天前展開
1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.
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