(1)MS degree or above with EE or CS background
(2)1 year experience or above in IC design/verification
(3)Familiar with SystemVerilog and Vera. Verilog or VHDL familiarity an advantage
(4)Good knowledge on Wireless communication or architecture.
(5)TCL/Perl coding experience is a plus
Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification