面議(經常性薪資達4萬元或以上) 新竹縣竹北市 5年工作經驗 1天前更新
• Define comprehensive DFT/test architecture for 3DIC and chiplet-based products, including pre-bond, mid-bond, post-bond, final test, and system-level test considerations.
• Develop test strategy for logic, memory, interconnect, TSV/micro-bump connectivity, repair, redundancy, and yield monitoring.
• Work with architecture, design, package, product engineering, reliability, and operations teams to ensure testability is built in from the beginning.
• Drive implementation planning for scan, MBIST, LBIST, boundary test, interconnect test, and diagnosis flows as applicable.
• Evaluate tradeoffs among coverage, test time, test cost, quality, and production scalability.
• Support ATE strategy, test access mechanisms, known-good-die methodology, and failure diagnosis for stacked or chiplet products.
• Establish DFT guidelines, test insertion requirements, and quality metrics for future 3DIC platforms.
• Lead bring-up and silicon learning feedback loop to improve yield and test effectiveness.
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