面議(經常性薪資達4萬元或以上) 新竹縣竹北市 5年工作經驗 1天前更新
• Define architecture and implementation strategy for die-to-die PHY driver, receiver, IO circuits, and ESD protection schemes for 3DIC products.
• Lead transistor-level and circuit-level design for high-speed, low-power interface blocks targeting chiplet and 3D integration applications.
• Optimize IO/PHY design for bandwidth, power, latency, signal integrity, area efficiency, and reliability.
• Develop ESD protection concepts compatible with fine-pitch micro-bump, TSV/interposer, and advanced package constraints.
• Drive design verification, corner analysis, reliability validation, and design signoff for IO/PHY/ESD circuits.
• Support technology evaluation for emerging die-to-die standards and internal interface solutions.
• Build reusable circuit IP, design guidelines, and implementation know-how for future programs.
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