面議(經常性薪資達4萬元或以上) 新竹市東區 4年工作經驗 40天前更新
1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:
* Scan chain insertion & ATPG pattern generation
* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
* Diagnosis to help manufacture process improvement
2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:
* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
* Develop & integrate DFT-related RTL design modules to test chip
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