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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 56天前更新展開
1. WiFi/BT/GPS/FM connectivity IC驗證及系統應用 2. PMIC or PCIe 系統設計及驗證 3. Connectivity 系統性能優化及驗證 4. Connectivity參考電路設計及驗證 5. 協助客戶量產過程時提供技術支援
- 面議（經常性薪資達4萬元或以上） 彰化縣員林市 工作經歷不拘 2天前更新展開
1.銷售公司提供之商品（免自行準備貨源） 2.對銷售工作有熱忱，喜歡與人互動 3.積極負責，具備團隊合作精神 4.需具備駕照，自備車輛佳 收入依能力與出勤率計算 多出勤、多努力 ＝ 多收入 *投履歷合適者會撥打電話聯繫面試時間*
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 56天前更新展開
1. 電源管理晶片架構與系統設計(手機/車用) 2. 低功耗設計技術開發 3. 混合訊號數位 IP 設計: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs 4. 電源管理晶片整合: front-end and back-end integration
- 面議（經常性薪資達4萬元或以上） 彰化縣彰化市 工作經歷不拘 2天前更新展開
1.銷售公司提供之商品（免自行準備貨源） 2.對銷售工作有熱忱，喜歡與人互動 3.積極負責，具備團隊合作精神 4.需具備駕照，自備車輛佳 收入依能力與出勤率計算 多出勤、多努力 ＝ 多收入 *投履歷合適者會撥打電話聯繫面試時間*
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 56天前更新展開
1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 2. 系統應用詳細電源需求與控制架構之分析與優化 3. 電源管理芯片規格制定與新技術之開發.
- 面議（經常性薪資達4萬元或以上） 台中市西屯區 工作經歷不拘 2天前更新展開
1.銷售公司提供之商品（免自行準備貨源） 2.對銷售工作有熱忱，喜歡與人互動 3.積極負責，具備團隊合作精神 4.需具備駕照，自備車輛佳 收入依能力與出勤率計算 多出勤、多努力 ＝ 多收入 *投履歷合適者會撥打電話聯繫面試時間*
全勤獎金年終獎金三節獎金激勵獎金員工聚餐 - 面議（經常性薪資達4萬元或以上） 新北市中和區 3年工作經驗 4天前更新展開
1. 會計帳務紀錄 2. 發票開立、對帳與報稅作業 3. 協助編製各項財務報表及憑證整理 4. 協助年度結帳、查帳及稅務申報 5. 主管交辦事項
就業保險產假產檢假員工生日禮金年終獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 56天前更新展開
1. 系統應用電源需求與控制架構分析 2. 電源管理晶片規格制定與驗證 3. 類比電路開發與驗證 4. 驗證電路板設計 5. 自動化測試開發
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 56天前更新展開
• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 56天前更新展開
1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 56天前更新展開
• Work with the architecture/micro-architecture/design teams to do white box testing. • Create testplans based on the micro-architecture document with the design team. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Build custom BFMs for co-sim based module level verification. • Add assertions and checkers to facilitate verification. • Work with the design team to do module level formal verification. • Create controlled random testcases. Pre-debug and provide debug reports. • Check functional coverage and code coverage.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 56天前更新展開
• Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 56天前更新展開
• Work with the architecture team in the early stage of the project to derive various architecture and micro-architecture proposals. • Work with the performance architect to create performance models for various functional blocks of a microprocessor, memory subsystem and the whole core. • Work with design teams to analyze performance corner cases and provide feedback to the architecture team.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 56天前更新展開
Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
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