- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 42天前更新展開
跨團隊合作(如:數位設計,系統應用, 測試, 製程...)以最佳化系統單晶片/平台競爭力及效能 ‧ 基於類比設計技術背景, 與類比設計團隊合作提供混合信號解決方案或IP, 以最佳化系統單晶片/平台競爭力及效能. 於計畫開發過程中, 協調類比團隊共同解決相關問題及克服挑戰, 以達成量產目標
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 42天前更新展開
1. Baseband algorithm development. 2. Ethernet PHY system architecture and algorithm design. 3. Communication system verification. 4. Architecture/algorithm design for low-power and high-speed communication system. 5. Digital signal processing of mixed-signal system.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 42天前更新展開
1. 旗艦智慧型手機晶片整合 2. 車用系統晶片整合 3. Clock架構 4. Timing收斂與分析 5. DFT/Test mode整合驗證
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 42天前更新展開
1. LCD Monitor IC相關的韌體開發 2. 影像處理相關應用與支援客戶產品開發 3. LCD Monitor周邊軟體tool開發
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 工作經歷不拘 42天前更新展開
1. 支援客戶產品的開發 2. LCD Monitor 或Retimer FW的開發與應用 3. 協助產品的推廣 4. LCD Monitor UI 的設計 以及訊號的處理
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 42天前更新展開
1. Work with design teams to do performance sign off in pre-silicon stage 2. ESL platform and simulation/emulation technology development. 3. Model development (includes behavior modeling/ cycle approximate modeling)
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 42天前更新展開
【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 42天前更新展開
由於先進製程與高整合度晶片需要較長的研發時間及高製造成本，DV (Design Verification) 已成為聯發科技晶片開發流程中不可或缺的一環。 CDG DV部門負責開發與執行最高整合度 Smartphone，TV與ASIC驗證工程。 內容包含:整合型驗證環境開發，大數據分析與效能改善，BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行。 工作中需要設計及精進Verification plan/methodology/bench，對SOC系統有整體而深入的了解。 利用最新EDA tool and concept來完成你的驗證計畫。 工作地點:新竹/台北
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 42天前更新展開
• 此職位屬於聯發科技modem客戶工程團隊，該團隊任務為與內部研發團隊合作，支援全球一流智能手機客戶的無線通訊技術(包括LTE、5G Sub-6GHz和5G mmWave技術)。 • 此職位主要職責在與客戶合作過程中帶領技術討論，並與內外部不同團隊合作，共同討論並解決客戶問題、滿足需求。 • 此職位需具備深入研究技術問題、了解客戶需求分析與功能開發的能力及良好應變能力。 • This is an exciting role in the MediaTek wireless technology group within the modem customer engineering team working with internal R&D team and support tier-1 global smartphone customers in wireless technologies (LTE, 5G Sub-6GHz, and 5G mmWave technologies) • You will play a key technical role in working with internal and external stakeholders to lead technical discussion and drive customer issues to resolution. • This is a dynamic position that will interact and collaborate with different teams and site location. • Ability to deep dive technical issues, understand customer requirement analysis and feature development. Looking for 4G/5G Modem Protocol / System Engineer with technical breadth in the protocol stack.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 42天前更新展開
We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.
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