- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 52天前更新展開
1. 測試硬體設計(Probe card, Load board, Socket) 2. 晶片驗證 3. CP/FT 測試程式開發 4. 量產維護
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 82天前更新展開
IC post Si activities coordination 1) Project post tape out schedule and production cost management 2) Change management and execution 3) NPI schedule control (ATE, SLT, qual) and tracking 4) Production capacity and test program readiness 5) MP schedule control and yield tracking IC post Si 專案管理 1）專案流片後進度及生產成本管理 2）變更管理執行 3）NPI進度控制（ATE、SLT、qual）和追蹤 4）生產能力和測試程序準備情況 5）MP進度控制和良率追蹤
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 82天前更新展開
1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification 4. Debug Architecture related IP design and integration
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 82天前更新展開
1. Responsible for high-speed UCIE development, including architecture definition, verification, and customer support (familiar with architecture, firmware, debugging, optimization, and testing tasks). 2. Define architecture and specifications through simulations. ( Matlab ) 3. Develop test automation. 4. Collaborate with the team to establish system prototypes and optimize performance. 5. Achieve product integration for clients and support mass production.
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 111天前更新展開
1. 無線網通系統, 數位設計 2. Micro Processor, 系統架構, low power/效能分析 3. SOC 整合/驗證 4. 工作地點:竹北/台北
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 173天前更新展開
1. Burn in process flow set up & qualification plan 2. Qualification failure electrical & physical analysis 3. Product reliability concern engagement with customer 4. New test supplier audit & qualification 5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.) 6. New product/technology introduction quality & reliability management 7. Testing house supplier quality improvement project
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 4年工作經驗 173天前更新展開
晶圓採購 & 成本控管 & 資訊整合 1.產能規劃&分配 2.詢價 談價 年度成本預測 3.主導晶圓廠相關會議 與內部事業部溝通會議 4.採購與成本相關專案管理
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 82天前更新展開
1. Expertise in managing critical IP technologies for HPC, such as high-speed interface, SerDes, D2D, 2.5D/3D, HBM, and advanced node process technologies, with a strong understanding of market dynamics 2. Investigate and analyze critical IP technology roadmaps, market trends and critical IP licensors business analysis as a basis to IP sourcing strategy forming 3. Mastering the decision-making groups, processes, key persons and underlying information circulated within major IP licensors, and driving substantial influence on their roadmap planning following corporate strategy 4. Leadership in collaborating with external partners, internal product marketing, internal engineers, business, financial and legal teams to proceed with on-target business negotiation and quality contract process management 1. 精於管理高效能運算（HPC）中的關鍵IP技術 (例如高速介面、SerDes、D2D、2.5D/3D、HBM等技術) 及先進製程相關技術、以及相關產業發展動態。 2. 調查並分析關鍵IP技術藍圖／市場趨勢，以及關鍵IP授權廠商之商務分析，作為制定IP採購策略的依據。 3. 掌握主要IP授權廠商之決策組織、流程、關鍵人員及資訊，配合公司策略，具體引導其相關藍圖規劃 4. 領導外部夥伴、內部產品行銷、內部工程、業務、財務及法務團隊的合作，完成符合技術合作目標之商務談判及合約管理
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 82天前更新展開
1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 82天前更新展開
1. 與業務使用者進行需求訪談與流程討論 2. IT 相關服務的專案管理 3. 公司商務領域的數位化（應用系統、人工智慧、數據）轉型 1. Engagement and Process Discussion with Business Users. (FIN domain) 2. Project Management on IT Service 3. Digitalization (application, AI, data) Transformation for business domain
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 20天前更新展開
1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 -建立並維護測試平台，進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果，協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板，支援系統驗證。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 173天前更新展開
As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan. It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan Work location: Hsinchu/Taipei
-
