- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 246天前更新展開
1. Work on 28nm~7nm design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution 1. Work on 28nm~7nm design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 246天前更新展開
We‘re looking for a Technical Writer / Document coordinator that focus on IC design macro and micro architecture documentation and document management. These documents would serve both internal requirement for cross team collaboration and external requirement for customers. The duties and responsibilities for this position include, but are not limited to: 1. Work closely with RDs, project teams, support teams, and other stakeholders to create and maintain high-quality documentation 2. Effectively manage documentation projects and deliver customer-focused documentation 3. Engage and collaborate with stakeholders to address content gaps, respond to direct feedback, and promote continuous improvement of the documentation experience 4. Master the use of our internal documentation toolchain, including document management system and the publishing platform 5. Develop content with a consistent and cohesive voice across all documentation 6. Ability to actively engage subject matter experts, and follow through on commitments with little supervision 7. Experience collaborating and directly interacting with globally-distributed stakeholders from diverse cultural backgrounds 8. Conduct trainings for RDs to improve technical writing skills *Only applicants with English resume will be considered, please submit/attach your English resume when applying this job.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 246天前更新展開
1. WiFi 無線通訊系統架構 2. WiFi IP數位設計 3. 計算機系統與周邊架構與數位設計 4. 系統晶片整合
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 246天前更新展開
- Explore timing degrade considering power integrity for proper signoff criterion - Explore EDA tool new features and introduce to project team - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 246天前更新展開
- Co-work w/ foundry/EDA vendors to define best PD imp recipes - Explore EDA tool new features and introduce to project team - Define proper FOM to project DTCO opportunities - Optimize PG structure for best resource and IR/EM concerns, including pillar types, via stacking layers - Help project team revise scripts, provide guidelines/checkers to check PD quality and feedback potential issues - Build physical-aware timing diagnosis utilities
- 時薪250~450元 新竹市東區 工作經歷不拘 246天前更新展開
• 參與3GPP RAN4會議，包括可能的線上或線下討論，以及協助撰寫會議技術文稿 • 檢驗內部及外部標準提案的有效性，透過鏈路級模擬或系統級模擬來撰寫技術文稿 • 於鏈路級模擬或系統級模擬程試中開發新的模組來支援最新3GPP標準的功能 • 參與內部或外部會議，提供想法創意，以及所需之效能評估
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 246天前更新展開
1. 數位電路開發設計與整合 2. IP與系統層級驗證，包含FPGA和實際晶片 3. 數位流程執行與優化 4. IP文件與功能維護
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 246天前更新展開
CPU Physical design, including 1. floorplan, P&R, CTS and timing closure 2. Physical verification
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 246天前更新展開
【職缺一】APR實體設計工程師 1. Working on advanced node design methodology, PD execution and sign-off 2. Develop advance clock tree structure 3. Able to handle complex APR with 500+ hardmacros 4. Project analysis in early stage 【職缺二】超大型SoC實體設計工程師 1. executing ultra-large scale SoC hierarchical physical design, in TOP level or GHz complex block level 2. Full experienced PD who can manage/coordinate other PDs‘ various number of hierarchical blocks 3. Flow development experience is a plus, to consolidate ultra-large scale SoC methodologies
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 246天前更新展開
高速與低功耗GPU實作(P&R), Power/Performance/Area/Schedule改善及FLOW開發 The candidate who fills this position will work closely with GPU hardware designer, IP and flow teams to improve GPU power/performance/area/schedule/yield. Candidate is responsible for all aspects of physical design and implementation of large GPUs which are targeted at the DTV, smart phone markets. Responsibilities include GPU hierarchical physical implementation/coordination (floor plan, block assembly, power/clock distribution, timing closure, power, IR, noise analysis and back-end verification). Also responsible for flow development with focus on improving GPU development schedule, chip cost, chip power, chip performance, yield, and development resources.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 246天前更新展開
擔任 數位IC設計團隊內的 計劃開發與控管工作 (Modem IP project lead) 1.規劃計劃開發的時程 與 檢視人力需求 2.追蹤RTL開發/驗證進度, 前/後段整合開發進度, 與APR狀況, 並控制品質 3.定期公告 各計畫狀態 4.與客戶溝通 開發團隊的 不良晶片分析狀況 Handling digital design team project development/ control jobs (Modem IP project lead) 1.Defining project schedule and resource 2.Tracking RTL development/verification status, front-end/back-end integration status and APR status, and control quality 3.Providing regular project status reports 4.Communication with client for fail chip analysis stoats
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