- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
職位與職責： 1. 定義 GPU 編譯器軟體架構及介面。 2. 開發/實作 GPU 編譯器流水線、連結以及各種最佳化/轉換。 3. 與驅動程式團隊及硬體團隊合作，實作新的 API 與硬體功能。 4. 與驅動程式團隊及硬體團隊合作，改善/調整效能與功耗。 5. 執行並交付專案，以達成里程碑與進度要求。 6. 分析並除錯程式碼生成相關問題。 7. 分析並影響未來 GPU 架構的設計。 8. 與內部及外部團隊建立可靠且值得信賴的合作關係。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 82天前更新展開
Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 82天前更新展開
加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。 - DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。 - ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。 - 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。 - 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。 - RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。 - 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 職務要求
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
1. 開發 Android smartphone multimedia video system framework, driver and functions 2. 架構設計、分析並優化 Android smartphone multimedia video 效能 3. Video 功能驗證 4. 系統架構設計與問題分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 82天前更新展開
We seek a skilled and visionary AI Computing Platform Software Planner to drive innovation and development across our AI platform products. This role requires close collaboration with leading technology partners – Google (Android OS), Microsoft (Windows) - to define, plan, and execute software features that enable advanced AI capabilities in our computing platforms. 1.Software Feature Set Planning & Decision Making 2.Execution Planning 3.Cross-Partner Collaboration 4.Platform Integration & Validation 5.Documentation & Communication
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 82天前更新展開
We are seeking a knowledgeable and analytical AI Computing Platform Hardware Planner to drive competitive benchmarking across CPUs, GPUs, and NPUs. This role requires deep familiarity with performance metrics—such as perf/W, tokens/sec—and industry standards. You will collaborate closely with QA teams to produce comprehensive insights comparing MediaTek’s computing platforms with leading competitors, including Intel, Qualcomm, and Apple. Key Responsibilities: 1. Competitive Benchmarking 2. Industry Knowledge and Analysis 3. QA Collaboration & Insight Generation 4. Reporting & Communication
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 82天前更新展開
1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 82天前更新展開
1. 資料中心AI晶片架構設計與RTL實作 2. 資料中心SoC與AI運算平台設計與驗證 3. 系統匯流排與AI週邊設計 4. SoC系統效能分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 82天前更新展開
1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis
- 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 82天前更新展開
We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 82天前更新展開
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 82天前更新展開
此職位高度重視執行力、組織協調以及所有ASIC設計的準時交付。 該職位負責協調涵蓋設計、驗證、PD、測試、DFT、封裝測試、營運和供應鏈等多個領域的複雜跨學科工作。 專案經理確保所有內部團隊從概念到生產全程保持一致，同時識別並克服所有風險和跨職能依賴關係。 This role is highly focused on execution excellence, organizational alignment and on-time delivery of all ASIC designs. This role coordinates complex multi-disciplinary efforts spanning, Design, Verification, Physical Design, Test Vehicles, DFT, Packaging Test, Operations and supply chain. The program manager insures that all internal groups are aligned from concept through production while identifying and overcoming all risks and cross functional dependencies.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 20天前更新展開
－Product marketing, planning, and strategy for AI data center products (e.g., Server CPU, AI accelerators/XPU, switch/networking products, optical interconnect) －Product lifecycle management, from ideation and requirements definition through development, launch, go-to-market, and end-of-life －Proactively identify new market opportunities and initiate new product concepts based on market trends, customer pain points, competitor analysis, and technology evolutions. －Develop and communicate clear value propositions and product stories that resonate with customers, stakeholders, and executive leadership. －Drive cross-functional alignment with engineering, business development, marketing, and support teams to successfully deliver and launch products. －Conduct deep market and competitive analysis to inform product strategy, pricing, and positioning. －Engage with key customers, industry leaders, and ecosystem partners to gather feedback, validate product ideas, and drive adoption.
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