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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 今天剛更新展開
The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 今天剛更新展開
***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 月薪40000~55000元 台南市柳營區 2年工作經驗 1天前更新展開
1. 負責工地職安衛事務、巡檢稽核及行政管理作業。 2. 執行安全會議、教育訓練、環境維護及改善追蹤。 3. 負責職安衛文件建檔、表單申請及資料維護。 4. 協助審查施工規劃與分包商施工前準備，確認符合法規及安全規範。 5. 追蹤現場安全缺失改善，並彙整相關紀錄。 6. 其他主管交辦事項。
家庭照顧假產假安胎假產檢假就業保險 - 月薪40000~55000元 台中市南屯區 2年工作經驗 1天前更新展開
1. 負責工地職安衛事務、巡檢稽核及行政管理作業。 2. 執行安全會議、教育訓練、環境維護及改善追蹤。 3. 負責職安衛文件建檔、表單申請及資料維護。 4. 協助審查施工規劃與分包商施工前準備，確認符合法規及安全規範。 5. 追蹤現場安全缺失改善，並彙整相關紀錄。 6. 其他主管交辦事項。
家庭照顧假產假安胎假產檢假就業保險 - 月薪40000~55000元 新竹縣竹北市 2年工作經驗 1天前更新展開
1. 負責工地職安衛事務、巡檢稽核及行政管理作業。 2. 執行安全會議、教育訓練、環境維護及改善追蹤。 3. 負責職安衛文件建檔、表單申請及資料維護。 4. 協助審查施工規劃與分包商施工前準備，確認符合法規及安全規範。 5. 追蹤現場安全缺失改善，並彙整相關紀錄。 6. 其他主管交辦事項。
家庭照顧假產假安胎假產檢假就業保險 - 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 今天剛更新展開
Role Summary: The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. Job Responsibility: －Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications. －Establish qualification requirements for new technology and product introduction. －Perform rigorous statistical analysis of reliability characterization data. －Enable high reliability during volume production by working with product groups to address risk areas. －Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. －Communicate study conclusions and recommendations to internal and external teams. Job Qualification: －Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. －Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). －Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. －Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM. －Must be curious, proactive, and detail-oriented. －Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 高雄市楠梓區 3年工作經驗 今天剛更新展開
Job Responsibilities - To be the owner for manufacturing test on the released products. - Responsible for test program introduce to mass production - Responsible for NPI (after R-gate released) test data analysis and feedback to BL/PETE if any improvement needed - To be the owner for duplicated test hardware by performing debug and qualification, MSC (Gage R&R) analysis and release report - Responsible for 1st line hold lot disposition, including low yield, QA fail .......etc - To initial and work with related process owners on testing processes, documentation, and best practices - Participate in or drive test automation initiatives when applicable Required Qualifications - 3+ years of experience as a Test Engineer - Solid understanding of software/system testing methodologies - Familiarity with Linux environments and command-line operations - Experience with machine language (e.g., Java, C++) - Experience in system, embedded, hardware, or manufacturing testing - Strong analytical and problem-solving skills - Strong sense of ownership and responsibility for product quality English communication, reading, writing
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 雲林縣褒忠鄉 1年工作經驗 4天前更新展開
1.產品可行性評估。 2.產品設計開發專案管理。 3.醫療器材技術文件撰寫。 4.設計開發查證與確效。 5.協助準備法規審查資料文件。 6.設計變更專案執行。 7.產品改良專案執行。 8.熟3D(Solidworks)/2D(CAD)繪圖軟體。 9.諳專利檢索與特徵分析鑑別新產品專利與規格資訊。 10.需不定期出差
- 面議（經常性薪資達4萬元或以上） 台北市南港區 2年工作經驗 今天剛更新展開
一、工作內容 想找一份穩定、單純、環境佳的工作嗎？ 我們正在招募 外商公司櫃台人員，適合喜歡接待、行政支援， 並具備基本英文溝通能力的你。 ．櫃台接待(含訪客/識別證/停車位/Locker/遺失物/郵務管理等) ．協助各節慶辦公室佈置 ．資產管理與盤點 ．部門文件、檔案、資料維護及管理 ．ESG相關活動、節慶相關活動主導或協助，與其他部門合作，例如會議、活動、訓練等 ．辦公室設施設備及環境維護管理，庶務相關備品管理及採購 ．其他主管交辦事項 二、時間：08:00-17:00 三、休假：週休二日，國定假日休 四、薪資：43,000~45,000元 五、福利 ．勞保、健保 ．年節獎金或禮券 ．結婚補助金與結婚禮金 ．生育補助金 ．年終獎金 ．公司負擔6﹪退休金 ．健康檢查 ．提供專業教育訓練及核發證照 ． 完整的人事管理與升遷制度
意外險家庭照顧假壽險員工結婚補助就業保險 - 月薪55000元 桃園市桃園區 5年工作經驗 1天前更新展開
1. 負責空調工程圖面繪製、修改及套圖作業。 2. 協助業主溝通、詢價作業及文書報表整理。 3. 執行設計圖、施工圖、竣工圖之檢視、修改與圖面清點。 4. 其他主管交辦事項。
家庭照顧假產假安胎假產檢假就業保險 - 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 今天剛更新展開
Please also apply on our platform: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/APAC-Foundry-Operations-Senior-Principal-Engineer_R-10062827 Job Description The APAC Foundry Operation team works with foundry partners on technologies which are evaluated and/or subjected to production. The key areas of responsibility of the jobholder are: - Lead the release and transfer of process options at foundries. - Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process - Lead and steer the projects towards timely completion to support NXP business needs. - Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc. The requirement fulfilling the job: - Bachelor or MSc in physics, material engineering or electrical engineering. In-depth knowledge of semiconductor physics, process development and manufacturing. - ＞10 years of experience with semiconductor process integration, working in foundries’ production or development teams. - Hands on experience in being a lead; leading teams with responsibilities in development, transfer or production projects. - All rounded knowledge on process integration, product testing, reliability testing, tapeouts, device physics will be needed in the discharge of duties as a project/ integration lead. - Good communication skills. - Pro-active working attitude, creative, pragmatic, enterprising and result driven. - Having the ability to influence and steer a discussion. - Familiar in managing/working with foundries, maximizing leverage from foundries.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 今天剛更新展開
Please also apply through: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/Tape-Out-Engineer_R-10063230 Role Overview, Responsibilities, and Qualifications The Tape Out Engineer plays a crucial role in the semiconductor design process, serving as the final checkpoint before integrated circuit designs are sent for fabrication. This position is responsible for ensuring that all physical and logical design data meet manufacturing requirements and quality standards, working closely with design, program managers, technologists, and manufacturing teams to resolve issues and optimize outcomes. Key Responsibilities 1. Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing. 2. Verify design integrity by reviewing database and documentation, and addressing any discrepancies or errors. 3. Work collaboratively with cross-functional teams, including design, technologists, program managers, and process engineering, to resolve technical issues and optimize designs for manufacturability. 4. Ensure all deliverables conform to foundry requirements. 5. Maintain detailed records of tape out procedures, revisions, and outcomes for future reference and process improvement. Qualifications 1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred). 2. Experience with physical design tools (e.g., Cadence, Synopsys) and semiconductor manufacturing workflows. 3. Excellent attention to detail, problem-solving skills, and ability to work under tight deadlines. 4. Willingness to work with flexible working hours to support critical Tape-outs. Effective communication in English for collaborating across technical teams. This role is ideal for individuals with a passion for precision and innovation, seeking to contribute to the successful launch of leading-edge semiconductor products.
分紅入股年終獎金三節獎金激勵獎金員工團保 - 月薪55000元 桃園市桃園區 5年工作經驗 1天前更新展開
1. 負責機電施工圖繪製、修改及套圖作業。 2. 協助業主溝通、詢價作業及文書報表整理。 3. 執行設計圖、施工圖、竣工圖之檢視、修改與圖面清點。 4. 其他主管交辦事項。
家庭照顧假產假安胎假產檢假就業保險 -
