-
職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 40天前更新展開
Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 40天前更新展開
Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 40天前更新展開
About the Role: Bring your GPU driver expertise and work closely with our Architecture and Micro-architecture teams. In this role, you will contribute across the GPU software stack and help extract maximum performance from the silicon while supporting the development of our next-generation GPU designs. This is not a siloed driver role. You will have opportunities to work across industry-standard graphics and compute APIs, kernel-mode drivers, GPU firmware, performance optimization, and hardware/software integration. What You‘ll Do — The Full Stack: • API Layer: Develop, debug, and optimize features for industry-standard APIs including Vulkan, DirectX, OpenGL ES, and OpenCL. • Kernel & Firmware: Work on kernel-mode drivers and GPU firmware to improve hardware control, stability, scheduling, memory management, and execution efficiency. • Performance: Analyze and optimize bottlenecks across the stack, including driver overhead, memory bandwidth, GPU scheduling, compute throughput, and power/performance tradeoffs. • Cross-Team Collaboration: Work closely with Architecture, Micro-architecture, Compiler, and GPU Model teams to validate GPU behavior, debug complex issues, and improve software/hardware interaction. • System-Level Debugging: Investigate issues across user-mode drivers, kernel-mode drivers, firmware, and hardware models to improve stability, correctness, and performance. Why This Role? • No Silos: You are not restricted to only one layer of the stack. You will have the opportunity to work across APIs, drivers, firmware, and performance. • Hardware-Software Impact: Your work will help the software stack fully utilize GPU hardware capabilities. • Next-Gen GPU Exposure: You will collaborate with architecture, compiler, and modeling teams on technologies that shape future GPU products. Ready to work across the entire GPU stack? Apply today.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 40天前更新展開
- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 40天前更新展開
Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 40天前更新展開
1. Mobile gaming and GPU technology planning, marketing and design-in for Smart Phone Product. 2. Customer relationship management. 3. Market & competition analysis.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 40天前更新展開
- Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. - System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 40天前更新展開
1. Chip integration and quality check 2. DFT insertion, verification and scan coverage analysis 3. Synthesis and PPA analysis
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 40天前更新展開
1. 數位 IC 設計（RTL/電路合成/整合/驗證） 2. SoC 層級晶片設計/整合 3. DFT 相關設計/規劃/整合 4. 靜態時序分析以及收斂 5. 設計流程開發與最佳化 6. 工作地點：台北/新竹
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 40天前更新展開
1. TOP 設計包含：微架構、設計、模擬、測試 - DFT top, PAD top 2. TOP 和感測器的整合和模擬包含： - eFUSE - PVT 感測器和 aging 感測器 - 整合 IO 到晶片中並滿足客戶需求 3. 測試流程、環境和程式開發
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 40天前更新展開
1. Direct manager and project lead 2. Cloud data center product 3. DFT task force 4. short term: top DFT flow implement and signoff long term: DFT/test mode planning and new tech development.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 40天前更新展開
- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 40天前更新展開
1. 定義供電架構並開發硬體/軟體協同設計技術與策略，以優化系統的電源效能。 2. 設計微處理器控制器和硬體電路，以及用於智慧型手機與車用產品電源控制相關設計的硬體輔助方案。 3. 進行耗電與時鐘樹分析，以發掘電源優化的機會。
-
