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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 3天前更新展開
1. 負責高速 Serdes相關開發, 包含驗證, 客戶支援 (熟悉架構, 韌體、除錯、優化及測試等工作項目) 2. 開發測試自動化 3. 協同團隊共同完成系統雛型建立及性能優化與調適 4. 達成客戶端產品導入，並支援產品量產
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 3天前更新展開
We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 3天前更新展開
The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 3天前更新展開
• Design, simulate and test various building blocks for photonic ICs such as modulators, filters, and detectors. • Develop mathematical models of photonic components for co-simulation with electronic circuits. • Contribute to the integration and testing of Photonic & Electronic ICs, collaborate with cross functional teams to improve system performance and optimize designs. • Must be proficient in programming (e.g. Python or MATLAB) for design automation
- 面議（經常性薪資達4萬元或以上） 新竹市東區 3年工作經驗 3天前更新展開
1.PCB power related hardware design：Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 2. System specification and design requirement collection. 3. System hardware verification and testing: function verification and power quality measurement. 4. Cross-organizational collaboration: Collaborate with IC design team, system team, SI/PI team, layout team, etc. to complete system design, production and verification. 5. Customer and related manufacturer support: including technical document writing, customer reference design support, on site support, etc.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 3天前更新展開
1. Develop Playbook for ASIC design 2. Monitor the project execution based on the Playbook 3. Coordinate among different teams to improve Playbook
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 3天前更新展開
1. 整合IR 資訊和內部團隊合作解決 IR 問題 2. 產生並分析 power 資訊 3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 3天前更新展開
1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 2. Memory controller/PHY Integration: Design and integration memory system.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 3天前更新展開
• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 3天前更新展開
1. Direct manager and project lead 2. Cloud data center product 3. DFT task force 4. 4.1Short term: top DFT flow implement and signoff 4.2Long term: DFT/test mode planning and new tech development.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 3天前更新展開
1. 負責晶片間（D2D & UCIe ) PHY IP硬體驗證與軟體開發。 2. 主導相關IP開發，熟悉ASIC專案中的軟體/SDK，能夠進行問題調試、最佳化和測試。 3. 與團隊合作，完成功能/系統啟動、驗證、效能最佳化和調整。 4. 實現產品設計導入，並支援產品量產。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 3天前更新展開
1. Familiar to 2.5D or 3D PKG integration & development & mass production experience 2. From chip architecture view to propose best-fit PKG technology with SIPI, testing, thermal consideration
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