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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 33天前更新展開
1.Responsible for technology and supply ecosystem planning in Data Center ASIC Testing Accessory domains. 2.Develop deep understanding of suppliers‘ technology capabilities, capacity planning, and roadmap direction to build strategic ecosystem insights. 3.Engage with R&D early during product definition and design phases to incorporate supply chain and manufacturing perspectives. 4.Ensure product design are aligned with future supplier technology readiness, capacity, and manufacturing capability during design phases. 5.Proactively identify technology and supply risks to enable scalable and competitive product solutions during design phases. 1.負責Data Center ASIC Testing Accessory領域之技術與供應鏈生態系規劃。 2.深入了解供應商技術能力、產能規劃及未來發展藍圖，建立關鍵技術供應鏈洞察。 3.於產品定義及Design階段即與研發團隊密切合作，導入供應鏈技術觀點。 4.於Design階段階段確保設計方向與未來供應鏈技術成熟度、產能及量產能力保持一致。 5.於Design階段識別技術與供應風險，協助打造具競爭力且可量產的產品解決方案。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 33天前更新展開
1.Responsible for technology and supply ecosystem planning in Data Center ASIC Packaging (Optical & Memory Integration) domains. 2.Develop deep understanding of suppliers‘ technology capabilities, capacity planning, and roadmap direction to build strategic ecosystem insights. 3.Engage with R&D early during product definition and design phases to incorporate supply chain and manufacturing perspectives. 4.Ensure product design are aligned with future supplier technology readiness, capacity, and manufacturing capability during design phases. 5.Proactively identify technology and supply risks to enable scalable and competitive product solutions during design phases. 1.負責Data Center ASIC Packaging (Optical & Memory Integration)領域之技術與供應鏈生態系規劃。 2.深入了解供應商技術能力、產能規劃及未來發展藍圖，建立關鍵技術供應鏈洞察。 3.於產品定義及Design階段即與研發團隊密切合作，導入供應鏈技術觀點。 4.於Design階段階段確保設計方向與未來供應鏈技術成熟度、產能及量產能力保持一致。 5.於Design階段識別技術與供應風險，協助打造具競爭力且可量產的產品解決方案。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 33天前更新展開
1.Responsible for technology and supply ecosystem planning in Data Center ASIC Memory domains. 2.Develop deep understanding of suppliers‘ technology capabilities, capacity planning, and roadmap direction to build strategic ecosystem insights. 3.Engage with R&D early during product definition and design phases to incorporate supply chain and manufacturing perspectives. 4.Ensure product design are aligned with future supplier technology readiness, capacity, and manufacturing capability during design phases. 5.Proactively identify technology and supply risks to enable scalable and competitive product solutions during design phases. 1.負責Data Center ASIC Memory領域之技術與供應鏈生態系規劃。 2.深入了解供應商技術能力、產能規劃及未來發展藍圖，建立關鍵技術供應鏈洞察。 3.於產品定義及Design階段即與研發團隊密切合作，導入供應鏈技術觀點。 4.於Design階段階段確保設計方向與未來供應鏈技術成熟度、產能及量產能力保持一致。 5.於Design階段識別技術與供應風險，協助打造具競爭力且可量產的產品解決方案。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 33天前更新展開
•Lead validation execution for fiber optic transceivers and optical engines used in AI and data center systems •Build and scale reusable optical test frameworks, automation software, and data analysis tools across multiple teams •Define and execute EVT and DVT plans, including characterization, regression, debug, and reporting •Support the reliability team with pre-/post-stress characterization, qualification support, and failure analysis •Validate key optical and link metrics such as Tx/Rx performance, BER, eye quality, jitter, TDECQ, sensitivity, optical power, wavelength behavior, and thermal stability •Drive root-cause analysis across optics, high-speed electrical interfaces, firmware, and test infrastructure •Improve design-for-test, measurement quality, and validation efficiency across programs •Provide technical leadership and mentorship across validation and test engineering
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 33天前更新展開
規劃並執行高速介面（如 PCIe, USB, DP）IP PHY 驗證。 建立並維護測試平台，進行 System 與 Electrical 測試。 使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 分析測試結果，協助 DE 及 SW 團隊解決問題。 設計並開發硬體 PCB 評估板，支援系統驗證。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 33天前更新展開
1. 開發 4G/5G/6G 實體層軟體 2. 開發射頻 (RF) 與數位前端 (DFE) 韌體及驅動程式 3. 通訊系統設計、實作與分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 6天前更新展開
Join our next-generation HPC SoC team to build cutting-edge Chiplet interconnect solutions. Whether you are an experienced architect or a recent graduate with strong fundamentals, this role offers a clear path to becoming a specialist in UCIe, D2D, and Advanced Packaging technologies. We value potential and provide the mentorship needed to grow into the role. 1. Develop Die-to-die and UCIe digital IP for HPC SOC. Design and implement robust digital IP blocks that enable high-bandwidth, low-latency communication across chiplets in complex HPC systems. 2. Integration of D2D controller and PHY to timing closure and DFT. Drive the integration flow between controllers and PHY layers, ensuring timing closure sign-off and implementing design-for-test strategies for manufacturing quality. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. Own the interface definition lifecycle, develop rigorous verification plans, and collaborate on physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers. Partner across disciplines to align on system-level goals, debug complex integration issues, and ensure seamless firmware-hardware co-design.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 33天前更新展開
1. Protocol design or debug on NR/LTE 2. Experience in IOT/field test 3. US, JP Chipset certification project management
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 33天前更新展開
1. 主導 tier1 電信商的 5G NR 數據效能分析及 issue triage 2. 設計並實作 AI 驅動的自動化分析工具與儀表板 3. 調查客戶回報問題並執行根因分析 4. 善用 AI 工具（Claude Code、GitHub Copilot、LLM）加速開發
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 63天前更新展開
開發聯發科技各種產品線所需之各種聲學處理或智能語音演算法： 1. 聲學或語音訊號增強演算法, 包括回聲消除, 噪音抑制, 或麥克風陣列訊號處理等 2. 智能語音演算法給語音介面之應用, 包括語音辨識, 語者辨識, 或語音喚醒等 3. 混合訊號聲學訊號處理演算法, 包括主動式噪音消除或是超聲波訊號處理
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 63天前更新展開
1. Architecture design and RTL implementation of Smartphone chipset 2. Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 63天前更新展開
負責 CPU silicon validation 相關軟體開發、code base 維護、patch 整合、驗證功能設計、平台調校與除錯。 支援 CPU silicon 功能驗證、軟體設定管理及跨層問題分析，確保 CPU 功能、效能、功耗、穩定性與驗證流程符合預期。 1.開發、維護與整合 CPU silicon validation 軟體、code base、patch 與自動化測試工具。 2.支援 CPU silicon 功能驗證、平台調校與 regression test，確認功能、效能及穩定性。 3.分析 HW/FW/SW log、register dump、trace 與測試結果，協同跨團隊定位問題、整合修正並驗證結果。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 63天前更新展開
1. 新設備評估 : 評估新購或擴產設備的技術規格、整體效能與投資回報率 2. 設備驗收 : 功能驗證與問題處理 3. 效能改善：分析產線設備稼動率（OEE），尋找提升產能與降低成本的方法。 1. New Equipment Evaluation: Assess the technical specifications, overall performance, and return on investment (ROI) of newly purchased or capacity-expanding equipment. 2. Equipment Acceptance: Functional Verification and Issue Resolution 3. Performance Improvement: Analyze production line equipment utilization (OEE) to identify ways to increase capacity and reduce costs.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 63天前更新展開
1. Workflow Analysis: Deeply engage with procurement and production planning teams to identify repetitive workflows, pain points, and high-value AI/automation opportunities. 2. AI Tool Development: Design, build, and maintain customized AI tools for the supply chain organization (e.g., automated RFQ/pricing analysis, schedule assistance, lead time prediction, and intelligent document/data search). 3. Adoption & Iteration: Provide user onboarding, documentation, and training to ensure team adoption; continuously iterate and enhance tool performance based on user feedback. 1. 痛點挖掘: 入了解採購與生管同仁之日常作業瓶頸, 識別適合 AI / 自動化賦能的應用場景. 2. 工具開發: 設計, 開發並維護供應鏈內部專用之 AI 應用工具 (如: 智能詢價比價, 生產排程輔助, 交期預測, 物料需求智能檢索等) . 3. 導入與推廣: 撰寫工具操作指引, 協助同仁上手使用, 並依據使用者回饋持續迭代優化工具效能.
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