- 面議（經常性薪資達4萬元或以上） 台北市大同區 3年工作經驗 29天前更新展開
職責要求 1.負責無塵室設計 任職資格 1.大學以上，日文N2具溝通能力 2.需有3年以上無塵室建設相關工作經驗 3.熟悉CAD(3D CAD佳)及BIM系統操作
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 台中市南屯區 3年工作經驗 29天前更新展開
職責要求 1.半導體晶圓廠施工管理 任職資格 1.專科以上，日文N2具溝通能力 2.具3年以上半導體工廠施工管理經驗 (電氣、給排水、空調等） 3.具電腦文書操作能力熟悉AutoCAD、CAD軟體及Word、Excel製作資料
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 月薪40000元 台北市大同區 工作經歷不拘 29天前更新展開
職責要求 1.半導體晶圓廠設計管理 任職資格 1.大學以上，日文N2具溝通能力 2.具半導體工廠設備設計實務經驗（電氣、給排水、空調任一設備設計） 3.熟悉CAD(3D CAD佳)及BIM系統操作
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 台北市中山區 3年工作經驗 29天前更新展開
職責要求 •自有客源與帶貨能力：需具備既有的貨主關係，特別是鋼鐵、礦產、穀物、肥料或大型機具設備商，能確保有即時的貨量貢獻。 •市場開發與議價技巧：散裝市場受 BDI 指數（波羅的海乾散貨指數）波動影響巨大，業務需具備敏銳的價格嗅覺，並能與船東及租家議價。 •具備大宗物質（Commodities）或專案貨（Project Cargo）操作經驗者優先錄取。 任職資格 •租船實務知識 (Chartering)：熟悉各種租船合約形式（如 Bare Boat Chater、Voyage Charter、Time Charter），並能理解合約條款（C/P Clauses）及法律風險。 •散裝貨物特性：了解非櫃裝貨物的裝卸要求、積載因素（Stowage Factor）及港口特性與限制（如吃水深度、吊桿設備、潮差等）。 •國際貿易法規：精通 Incoterms、信用狀（L/C）以及提單（B/L）的操作實務。 •外語流利度：具備多益750分以上或其他國際英檢相同等級以上，優秀的英文讀寫能力及口說能力（國際船東/貨方/港口代理間聯繫）。 •資歷要求：要求 3-5 年以上的航運業相關經驗，有明確的散裝操作或業務經驗。 •學歷背景：航運管理、國際貿易、國際運輸相關系所優佳。 •抗壓性與機動性：散裝業務需配合全球時差與船舶進港時間，常需 24/7 隨時處理突發狀況。
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 台中市南屯區 工作經歷不拘 29天前更新展開
職責要求 1.熟悉主軸結構，含軸承、馬達、潤滑及冷卻系統 2.具備機械裝配、精密儀器操作能力、基礎機電知識、工具量具、CNC相關知識與經驗 3.主軸與二軸頭檢查故障診斷分析維修， 針對異常處理能獨立作業 4.依據規範要求，執行故障分析、檢查檢修、報告與系統平台作業、案件管理 5.客戶關係管理，關鍵客戶溝通應對 任職資格 1.機械、電機或相關科系為佳。 2.具備基礎機械製造或數控機械維護知識 3.具備閱圖基礎機械/電氣圖之能力 4.基礎英文能力，能與廠商專業技術人員溝通討論 特質: 1.具備問題分析與現場處理能力 2.良好溝通與客戶服務態度, 能與客戶保持專業互動
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 30天前更新展開
職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 30天前更新展開
職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 30天前更新展開
職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 7年工作經驗 30天前更新展開
職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 面議（經常性薪資達4萬元或以上） 高雄市左營區 工作經歷不拘 30天前更新展開
職責要求 1.辦理電力系統相關工程技術，需熟悉電驛保護協調、電力相關標準，並執行型態管理，以確保設備設計功能正常、維持營運安全。 2.協辦電力系統升級、置換等相關工程之技術研擬及現場管理作業，包含招標及技術文件撰稿、現勘、監工、測試、點移交作業等。 3.系統性設備異常營運與維修技術支援，需與採購、設備介面單位及契約承商等協作，執行專案工程履約管理作業，確保工程契約符合安全準則。 4.協助評量施工與測試作業風險，規範風險減輕需求。 5.分責承辦部門工程合約之設計審查、意見彙整與澄清、介面與排程協調、施工與測試監察進度管控與彙報等合約執行作業項目。 6.依公司政策，辦理與其他機關單位之技術協助與相關業務。 任職資格 1.大學以上，電機電子工程相關系所，英文中上可溝通及閱讀英文文件 2.具高考電機工程技師尤佳 3.熟悉工程專案管理作業與一般採購合約流程與管理 4.熟悉軌道供電系統相關子系統包括：變電系統、輸電系統、電力監控系統、配電系統及道旁機電系統等
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 - 月薪30000~40000元 新北市板橋區 工作經歷不拘 2天前更新展開
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就業保險產假產檢假安胎假家庭照顧假 - 月薪35000元 台北市中正區 工作經歷不拘 28天前更新展開
工作內容： (1) 定期客戶服務 (2) 處理勞工生活上、工作上發生的問題及任何突發狀況，協助勞雇雙方溝通協調 (3) 文件翻譯 (4) 勞工在台相關文件辦理 (5) 配合公司內部作業相關表單填寫 (6)機動協助辦理其他主管交辦任務
產假家庭照顧假全勤獎金員工生日禮金年終獎金 - 面議（經常性薪資達4萬元或以上） 台北市大安區 8年工作經驗 34天前更新展開
職責要求 1. 負責新產品開發策略規劃與執行，確保時程、品質與成本達成目標 2. 領導研發團隊（設計/工程），進行專案管理與資源整合 3. 建立與優化研發流程，確保符合 ISO 與產品開發規範 4. 審查產品設計圖面、規格書與 BOM，確保設計正確性與量產可行性 5. 跨部門整合業務、市場與生產需求，推動產品落地 6. 負責供應商技術管理與外部資源整合 7. 推動產品創新與技術優化 8. 建立團隊人才培育機制，提升整體研發效能與績效 9. 規劃專利佈局與技術資產管理 10. 主導各國法規符合性、產品測試與認證專案 11. 負責新產品導入量產（NPI），確保開發順利銜接製造端 任職資格 1.工作經歷:8年以上、其中3年設計主管經驗(帶過2人以上團隊) 2.工業設計、商業設計、產品設計相關科系優先，具備產品設計與開發實務經驗 3.熟悉ISO9001或其他品質管理流程者、及具PLM產品管理系統經驗者佳 4.具備良好溝通協調能力與跨部門合作經驗 5.邏輯清晰，具備創新思維與問題解決能力 6.對工作有責任感，態度正向積極、抗壓性佳、負責、企圖心、持續學習力 7.具良好溝通協調能力。 8.擅長工具: AUTO CAD、CREO
國內、外旅遊補助生育補助年終獎金員工團保三節獎金 -
