- 月薪41000~80000元 桃園市龜山區 2年工作經驗 2天前更新展開
1. 政策管理： ● 執行資訊安全相關稽核作業 ● 資安事件、漏洞缺失追蹤與改善 ● 資訊安全政策相關文件統整與維護 ● 資安教育訓練與資安宣導 2. 技術管理： ● 資訊安全相關專案追蹤與規劃 ● 風險評估執行與彙整
員工結婚補助員工及眷屬喪葬補助就業保險產假產檢假 - 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 2天前更新展開
1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development 3. Common strip format unification management 4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) 5. PCB technology development and DRM owner
- 面議（經常性薪資達4萬元或以上） 台南市永康區 2年工作經驗 2天前更新展開
1.鋁合金壓鑄產品開模前設計方案檢討。 2.模具加工進度控管，模具試產排程控管。 3.模具加工尺寸與特徵檢查。 4.參與試模檢討、修模報告製作與圖面修改。 5.未來有意願學習半固態成型技術。
就業保險產假產檢假安胎假家庭照顧假 - 月薪43000~48000元 台北市文山區 工作經歷不拘 2天前更新展開
1. 具護理師執照，執行上針、抽血 2. 向病患衛教及解釋細胞治療的相關流程 3. 聯絡醫師、病患及廠商，安排回輸和採血的時間 4. 借用治療場地，並聯絡病患和廠商到院執行治療 5. 協助細胞治療中心的相關行政業務，例如：計畫申請/修正送審衛福部、電子公文、費用 請款……等 6. 業務統計分析 7. 主管交辦事務
尾牙員工在職教育訓練產假產檢假員工健身房 - 面議（經常性薪資達4萬元或以上） 台南市永康區 2年工作經驗 2天前更新展開
1.協助試作期間模具生產事宜、模具架設、前後置作業。 2.協助試作期間機台參數調整。 3.協助試作期間自動噴霧程式(ABB)調整。
就業保險產假產檢假安胎假家庭照顧假 - 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 2天前更新展開
1. SoC IC implementation 規劃設計 2. DFT 規劃設計 以及timing closure signoff 3. 設計方法流程開發及優化 4. 工作地點:新竹/台北
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 2年工作經驗 2天前更新展開
1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗，提供不同的職級
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 2天前更新展開
1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 2天前更新展開
1. Develop Ethernet MAC for HPC networking applications. 2. Work closely with architecture, verification and physical teams from specification to implementation.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 4年工作經驗 2天前更新展開
1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 8年工作經驗 2天前更新展開
1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 2天前更新展開
【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
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