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職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 1天前更新展開
1. Processor micro-architecture design 2. Cache and bus interface 3. DSP and machine learning library design 4. Simulator/modeling and architecture
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 1天前更新展開
Job Description: (1) Sourcing for IC backend(assembly & testing) : Cost management and logistics control, optimizing the outsourcing strategy between cost and supply for constant operation requirement. (2) Building up working model of a new project‘s capacity/cost with effective plan (3) Regular meeting with OSATs and keep strategic relationship on constant production support and long-term cooperation (4) Monitor market trend and study valuable source for next-step of OSAT requirement on cost and technical development. (1) IC 後段封裝測試採購 : IC 後段成本管理與運籌布局，對公司持續營運維護最佳化的成本與產能策略。 (2) 建立專案產能與成本評估模式 (3) 常規會議與封測廠維持產能支援與長期合作的策略關係 (4) 監督市場走向並研究對成本優化與技術發展具價值的產能來源
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
1.RTL platform design integration (clock/reset/power/bus design and architecture, MBIST, etc.) - use for FPGA and Emulator should also be considered 2.Integration quality check (RTL/SDC/Power spec signoff check)
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
1.Propose design verification plan and do the execution based on IP and system HW architecture/application 2.Develop design verification environment 3.Develop required verification methodology and adopt into project 4.Develop HW emulator/FPGA platform to accelerate design verification task 5.Co-work with SW/HW engineering to valid function and shift-left SW develop 6.Debug and root cause failure with SW/HW engineering in both pre-silicon and post-silicon
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 1天前更新展開
• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows. • Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy. • Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug. • Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation. • Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL. • Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug. • Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities. • Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases. • Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols. • Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 1天前更新展開
We need your help drive the development of Computing technology for architectures used for artificial intelligence, high-performance computing, gaming. Come join the Computing Platform team and help us push performance boundaries for all our products! At MTK, our mission is to build great products that accelerate next-generation computing experiences—for PCs and other derived systems. What you‘ll be doing: • Benchmark MTK solutions against x86 and ARM offerings the same timeframes to frame MTK‘s value proposition, and suggest software or hardware improvements. • Present insights and recommendations to MTK senior leadership. • Build a strong knowledge base of long-term roadmap requirements to support product definitions to meet next-gen edge AI computing platform needs. • == • Work on workload bring-up and performance analysis/projection, both on silicon and full-system. • Study real world use-cases and identify critical application behavior for PC and Edge AI Market, including PC/Laptop productivity , Gaming, Creating workloads • Work with CPU and interconnect architects to improve future SoC and system designs based on your findings.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 1天前更新展開
我們的使命是協助公司將生成式 AI（Generative AI）有效導入日常工作流程，推動員工提升工作效率與創新能力。 此職位將擔任技術團隊與業務單位之間的橋樑，協助規劃 AI 導入策略、設計賦能活動、推廣最佳實務，並蒐集使用者需求與回饋，持續優化 AI 工具的應用成效。 我們期待對 AI 技術充滿熱情，具備優秀溝通能力與推動能力的人才，一同加速企業 AI 轉型。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 1天前更新展開
1. Optimize 6G/5G modem architecture and associated hardware/software flows in aspects of system performance/power/area (PPA) to improve product competitiveness. 2. Develop architectural simulation, system-level modeling, and analysis platforms for modem baseband system performance, low-power optimization, and hard real-time (HRT) latency analysis. 3. Collaborate closely with domain architects to deliver quantitative reports based on simulation data, driving key architectural decisions. 1. 優化 6G/5G 解調架構及相關的硬體/軟體流程，提升系統效能／功耗／面積（PPA），增強產品競爭力。 2. 開發架構模擬、系統級建模與分析平台，用於評估基帶系統效能、低功耗優化與硬實時（HRT）延遲分析。 3. 與領域架構師緊密合作，根據模擬數據產出量化報告，推動關鍵架構決策。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 1天前更新展開
參與 5G/6G New Radio 行動通訊數位基頻 IC 與 IP 開發. 包括multi-RATs (2/3/4/5/6G) modem的架構設計, RTL 設計, 整合和驗證.
- 月薪40000元 台南市安平區 1年工作經驗 1天前更新展開
🌱【蔬果子蔬食料理｜誠徵正職夥伴】🌱 想找一份 薪資穩定、制度清楚、福利完整 的餐飲工作嗎？ 歡迎加入蔬果子團隊 ❤️ 💰【薪資待遇】 ・月薪 $32,500 起 ・全勤獎金 $1,000／月 ・加班費另計，依《勞動基準法》規定計算 ・依門市營運需求安排加班，加班時數依實際狀況而定 ・另有考核獎金 ・另有業績達標獎金 ・薪資固定以銀行轉帳方式發放 🔥 正常出勤並配合加班，每月薪資約可達 $40,000～$60,000 ※ 實際薪資依當月加班時數、出勤狀況及獎金有所不同。 ⏰【工作時間】 09：30－14：00 15：00－20：00 中間休息 1 小時 採排班制，依門市營運需求安排加班。 📅【休假／特休制度】 ・見紅休（採排班方式安排休假） ・到職滿半年享特休 3 天 ・到職滿一年享特休 7 天 ・其他休假依勞動基準法相關規定辦理 ❤️【員工福利】 ・依法投保勞保、健保 ・提供員工餐 ・全勤獎金 $1,000／月 ・考核獎金 ・業績達標獎金 ・完整工作 SOP 及教育訓練 ・提供升遷及職涯發展機會 👩🍳【工作內容】 ・依公司 SOP 完成餐點製作及出餐 ・協助顧客點餐、包餐及外場服務 ・協助備料、補貨及物品整理 ・維持廚房、工作區及門市環境清潔 ・遵守食品安全及衛生管理規範 ・配合團隊完成每日門市營運工作 ・完成主管交辦事項 🌟【我們希望你】 ✔️ 工作穩定、有責任感 ✔️ 願意配合排班及加班 ✔️ 重視環境整潔與食品衛生 ✔️ 願意遵守公司 SOP 及管理制度 ✔️ 具餐飲相關工作經驗者佳 ✔️ 願意學習、重視團隊合作 ✔️ 希望長期穩定發展者 🌿【加入蔬果子】 月薪 $32,500 起 ＋全勤獎金 $1,000 ＋依法計算加班費 ＋考核獎金 ＋業績達標獎金 🔥 每月薪資約 $40,000～$60,000 ※ 依實際加班時數、出勤及獎金而有所不同。 享有勞健保、員工餐、特休及完整教育訓練制度。 如果你願意認真學習、配合團隊，想找一份收入穩定、制度完整，也有發展機會的工作，歡迎加入 蔬果子蔬食料理 ❤️🌱
- 面議（經常性薪資達4萬元或以上） 新竹市東區 10年工作經驗 1天前更新展開
• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.
- 面議（經常性薪資達4萬元或以上） 新北市土城區 工作經歷不拘 1天前更新展開
1.負責收入、費用、應付帳款及固定資產等相關帳務處理及相關報表編製。 2.銀行往來作業/日常現金收付。 3.職工福利委員會帳務處理及相關稅務申報。 4.固定資產帳務處理。 5.營業稅資料核對、調節及申報作業。 6.負責各類所得資料彙整、扣繳申報及相關調節表編製。 7.會計師查帳資料整理及提供。 8.協助主管交辦事項。
員工在職教育訓練良好升遷制度年節獎金員工生日禮金年終獎金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 1天前更新展開
•重點開發技術: 系統開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產，有SLT的經驗 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範
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