面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘 今天剛更新
RTL coding - Required
• Proficient in SystemVerilog and Verilog HDL for synthesizable RTL精通 SystemVerilog 和 Verilog HDL,能夠寫出可綜合的 RTL 程式碼
• Solid understanding of synchronous design, clocking, and reset strategies紮實的同步設計、時脈控制與重設策略知識
• Experience with clock domain crossing (CDC) techniques and metastability handling具備時脈域交叉 (CDC) 技術與亞穩態處理經驗
• FSM coding, pipelining, and retiming for timing closure熟悉有限狀態機 (FSM) 編碼、管線和時序重整化以實現時序收斂
• Familiarity with low-power techniques: clock gating, isolation cells, retention flops熟悉低功耗技術:時脈門控、隔離單元、保持觸發器
• Writing RTL that meets area, power, and performance (PPA) targets能夠編寫滿足面積、功耗和效能 (PPA) 目標的 RTL 程式碼
Microarchitecture - Required
• Ability to implement designs from a microarchitecture specification能夠根據微架構規範實現設計
• Working knowledge of AMBA protocols: AXI4, AHB-Lite, APB熟悉 AMBA 協定:AXI4、AHB-Lite、APB
• Understanding of data path design, FIFOs, arbiters, and flow control logic理解資料通路設計、FIFO、仲裁器和流控制邏輯
• Familiarity with SoC integration concepts: interrupts, address maps, register files熟悉 SoC 整合概念:中斷、位址對映、暫存器文件
• Experience writing or contributing to microarchitecture specification documents具備編寫或參與微架構規範編寫的經驗文檔
Functional verification Required
• Experience writing directed and self-checking RTL testbenches in SystemVerilog具備使用 SystemVerilog 撰寫定向與自我檢測 RTL 測試平台的經驗
• Familiarity with UVM methodology; ability to develop UVM agents or sequences熟悉 UVM 方法論;能夠開發 UVM 代理或序列
• Able to interpret coverage reports and drive functional coverage closure能夠解讀覆蓋率報告並推動功能覆蓋率的收斂
• Experience using simulation tools (VCS, Questa) for debug and regression具備使用模擬工具(VCS、Questa)進行調試和回歸測試的經驗
• Exposure to formal property verification (assertions, assumptions, cover points) 熟悉形式化屬性驗證(斷言、假設、覆蓋點)
Design sign-off - Required
• Reading and interpreting STA reports; understanding setup/hold slack and critical paths能夠閱讀和解讀 STA 報告;理解建立/保持時間裕量和關鍵路徑
• Awareness of CDC and RDC lint checks; able to resolve common violations了解 CDC 和 RDC 代碼檢查;能夠解決常見違規問題
• DFT awareness: scan chain insertion, test mode design considerations了解 DFT:掃描鏈插入、測試模式設計注意事項
• Ability to work with PD feedback and make RTL changes to resolve place-and-route issues能夠根據 PD 回饋進行 RTL 修改,以解決佈局佈線問題
展開 國內、外旅遊補助生育補助年終獎金員工團保三節獎金