- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 今天剛更新展開
Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 今天剛更新展開
Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications
- 面議（經常性薪資達4萬元或以上） 高雄市梓官區 工作經歷不拘 今天剛更新展開
1. 作業現場架設警示標語與設置安全圍欄，確保現場人員與設備安全。 2. 依照操作規範操作堆高機進行貨物裝卸、堆放及運輸作業。 3. 定期執行堆高機機具的日常保養和檢查維修計畫，保持設備正常運行。 4. 針對機具的零件與耗材進行除鏽、上油、防護及定期清潔作業。 5. 協助檢查貨物包裝完整性與正確性，確保物品於搬運中完好無損。 6. 聽從現場主管的指揮，並遵循所有的安全作業規範及SOP指導。 ********需配合加班 無法加班者請勿應徵********
產假產檢假全勤獎金年節獎金員工生日禮金 - 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting
- 面議（經常性薪資達4萬元或以上） 新竹市東區 2年工作經驗 今天剛更新展開
About the Role: Bring your GPU driver expertise and work closely with our Architecture and Micro-architecture teams. In this role, you will contribute across the GPU software stack and help extract maximum performance from the silicon while supporting the development of our next-generation GPU designs. This is not a siloed driver role. You will have opportunities to work across industry-standard graphics and compute APIs, kernel-mode drivers, GPU firmware, performance optimization, and hardware/software integration. What You‘ll Do — The Full Stack: • API Layer: Develop, debug, and optimize features for industry-standard APIs including Vulkan, DirectX, OpenGL ES, and OpenCL. • Kernel & Firmware: Work on kernel-mode drivers and GPU firmware to improve hardware control, stability, scheduling, memory management, and execution efficiency. • Performance: Analyze and optimize bottlenecks across the stack, including driver overhead, memory bandwidth, GPU scheduling, compute throughput, and power/performance tradeoffs. • Cross-Team Collaboration: Work closely with Architecture, Micro-architecture, Compiler, and GPU Model teams to validate GPU behavior, debug complex issues, and improve software/hardware interaction. • System-Level Debugging: Investigate issues across user-mode drivers, kernel-mode drivers, firmware, and hardware models to improve stability, correctness, and performance. Why This Role? • No Silos: You are not restricted to only one layer of the stack. You will have the opportunity to work across APIs, drivers, firmware, and performance. • Hardware-Software Impact: Your work will help the software stack fully utilize GPU hardware capabilities. • Next-Gen GPU Exposure: You will collaborate with architecture, compiler, and modeling teams on technologies that shape future GPU products. Ready to work across the entire GPU stack? Apply today.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 今天剛更新展開
加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。 - DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。 - ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。 - 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。 - 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。 - RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。 - 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 職務要求
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 工作經歷不拘 今天剛更新展開
1. Android平台相關軟體問題，SCM, Code line管理等...主要客戶聯絡窗口。 2. 分析、釐清並解決或轉交客戶回報的系統層級問題。 3. 進行問題根因分析，並提供即時解決方案或替代方案。 4. 與內部工程團隊協作，確保問題有效解決。 5. 進行Android系統的性能分析與優化。 6. 支援Android平台的整合，包括問題排查、除錯與驗證。 7. 撰寫問題分析、解決方案及實踐文件，供內外部參考。 8. 與國內外客戶（包含美國）有效溝通，了解需求並提供技術支持。 9. 參與客戶會議、技術討論及專案檢討等相關活動。
- 月薪43000~43000元 新北市中和區 工作經歷不拘 今天剛更新展開
工作內容： • 監控與應變 • 訪客接待 • 收發文件 上班資訊： • 地點：新北市中和區中興街 • 班別：日班 07:00~9:00 • 月休：大月休7天、小月休6天 福利與保障： • 勞保、健保、6％勞退提撥、團保 適合這樣的你： • 想找穩定長久、單純的工作 • 個性穩定、守時、好相處
需穿著員工制服良好升遷制度意外險員工結婚補助員工及眷屬喪葬補助 - 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 今天剛更新展開
1. 開發 Android smartphone multimedia video system framework, driver and functions 2. 架構設計、分析並優化 Android smartphone multimedia video 效能 3. Video 功能驗證 4. 系統架構設計與問題分析
- 月薪42000~48000元 新竹縣竹北市 工作經歷不拘 今天剛更新展開
1. 負責建築物及周邊環境的夜間巡邏，確保門窗安全檢查完好及環境安全無虞 2. 監控出入人員之動向及活動，運用監控設備進行可疑活動的監控和報告 3. 回應並迅速處理警報事件，採取緊急應變措施以防止入侵、竊盜及其他安全事故 4. 具備消防及安全程序的知識，熟悉急救基本技能，能在緊急狀況下提供支援 5. 負責鑰匙和門禁管理，熟悉監控設備操作，確保設施安全運作 6. 維護並管理安全事件的紀錄與報告，遵守公司安全政策及程序 7. 提供現場住戶或員工的基本指引與協助，處理訪客登記及引導服務 期待您的加入，與我們一起保障科技廠的安全和穩定，立即投遞履歷吧！
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