面議(經常性薪資達4萬元或以上) 新竹縣竹北市 5年工作經驗 今天剛更新
• Define and drive PI/SI/Thermal signoff methodology for 3DIC, chiplet, and advanced packaging programs.
• Lead end-to-end analysis for power delivery network, high-speed signal channels, and thermal/mechanical interaction across die-package-system.
• Establish signoff criteria, design margins, modelling quality standards, and correlation flow for simulation versus silicon or lab measurements.
• Work closely with package design, bump/TSV planning, PHY/IO, floorplan, architecture, and product engineering teams to resolve integration issues early.
• Identify and mitigate risks related to IR drop, SSN, jitter, crosstalk, insertion loss, return loss, EMI/EMC, hotspot formation, and thermal coupling.
• Drive EDA vendor and tool engagement for modelling, extraction, co-simulation, and signoff automation.
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