-
職缺名稱公司名稱上班地點工作經驗更新薪資待遇
- 面議（經常性薪資達4萬元或以上） 台北市內湖區 8年工作經驗 1天前更新展開
1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 1天前更新展開
•重點開發技術: 系統軟韌體開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 1天前更新展開
1. 負責高速UCIE,SERDES相關開發, 包含架構定義, 驗證, 客戶支援(熟悉架構, 韌體、除錯、優化及測試等工作項目) 2. 透過模擬來定義架構與規格 ( Matlab ) 3. 開發測試自動化 4. 協同團隊共同完成系統雛型建立及性能優化與調適 5. 達成客戶端產品導入，並支援產品量產
- 面議（經常性薪資達4萬元或以上） 新竹市東區 4年工作經驗 1天前更新展開
1. 熟悉 2.5D 或是 3D 封裝技術, 開發和量產經驗 2. 從系統架構優劣比較, SIPI 或是測試或是 thermal 角度來提供適合的封裝技術
- 面議（經常性薪資達4萬元或以上） 新竹市東區 5年工作經驗 1天前更新展開
1. Develop 3.5D methodology from RTL to GDS and Package 2. Coordinate Thermal and PI/SI team to deal with high power design 3. Execute the project at different phases
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
1. 高速Serdes系統技術開發(200Gbps+), 包括電通訊與光通訊(optical interconnect) 2. 定義系統技術規格並與設計團隊(Analog, Digital, Algorithm)討論系統架構, 建立模型模擬評估 3. Serdes 關鍵技術評估與開發( e.g., Next Gen Serdes, optical nonlinearity compensation, CPO technology) 4. 協助Serdes IP驗證問題分析
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 1天前更新展開
1. 應用於I/O 小晶片的 SerDes 設計驗證工作. 包含從原型測試到量產晶片, 並與類比, 數位和演算法設計團隊合作. 2. 負責實現 SerDes 韌體設計, 以驗證連線效能和實現量產測試 3. 負責建立自動測試和資料分析, 以測試SerDes的晶片特性和分析失效晶片
- 面議（經常性薪資達4萬元或以上） 新竹縣竹北市 2年工作經驗 1天前更新展開
1. 負責高速 Serdes相關開發, 包含驗證, 客戶支援 (熟悉架構, 韌體、除錯、優化及測試等工作項目) 2. 開發測試自動化 3. 協同團隊共同完成系統雛型建立及性能優化與調適 4. 達成客戶端產品導入，並支援產品量產
- 面議（經常性薪資達4萬元或以上） 新竹市東區 8年工作經驗 1天前更新展開
We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 6年工作經驗 1天前更新展開
The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.
- 面議（經常性薪資達4萬元或以上） 新竹市東區 工作經歷不拘 1天前更新展開
• Design, simulate and test various building blocks for photonic ICs such as modulators, filters, and detectors. • Develop mathematical models of photonic components for co-simulation with electronic circuits. • Contribute to the integration and testing of Photonic & Electronic ICs, collaborate with cross functional teams to improve system performance and optimize designs. • Must be proficient in programming (e.g. Python or MATLAB) for design automation
-
