面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘 今天剛更新
職責要求
RTL Coding Required
• Expert-level SystemVerilog / Verilog HDL for synthesizable RTL精通 SystemVerilog/Verilog HDL,能夠寫出可綜合的 RTL 程式碼
• Deep understanding of clocking, reset strategies, and clock domain crossing (CDC) 深入理解時脈、重設策略和時脈域交叉 (CDC)
• Proficient in finite-state machine (FSM) design and pipeline microarchitecture精通有限狀態機 (FSM) 設計與管線微架構
• Low-power design techniques: clock gating, power gating, multi-Vt, retention flops低功耗設計技術:時脈門控、電源閘控、多閾值電壓 (Vt)、保持觸發器
• Experience coding to timing closure constraints and meeting PPA targets具備根據時序收斂限制進行編碼並達到 PPA 目標的經驗
Microarchitecture Required
• Ability to own microarchitecture spec from concept to sign-off能夠獨立完成從概念到最終定稿的微架構規範
• Strong grasp of on-chip interconnects: AXI4, AHB-Lite, APB, TileLink, CHI/ACE精通片上互連:AXI4、AHB-Lite、APB、TileLink、CHI/ACE
• Cache coherency, memory subsystem, and NoC design experience具備快取一致性、記憶體子系統和片上網路 (NoC) 設計經驗
• Skilled in defining and documenting microarchitecture specification documents能夠定義和編寫微架構規範文檔
• Ability to drive design partitioning and IP integration at SoC level能夠在 SoC 層級推動設計劃分和 IP 集成
Functional Verification Required
• Familiarity with UVM / OVM testbench methodology熟悉 UVM/OVM 測試平台方法
• Ability to write self-checking RTL testbenches能夠撰寫自我檢測測試RTL 測試平台
• Coverage-driven verification planning and closure覆蓋率驅動的驗證規劃與收尾
• Experience with formal property verification (JasperGold, VCFormal) 具備形式化屬性驗證經驗(JasperGold、VCFormal)
Design Sign-off Required
• Static timing analysis (STA) review and ECO coordination靜態時序分析 (STA) 審查和工程變更協調
• CDC / RDC lint and equivalence checking (Conformal, Spyglass) CDC/RDC 程式碼檢查和等效性檢查(Conformal、Spyglass)
• DFT-aware design: scan insertion, BIST, JTAG / boundary scan考慮可設計性的設計:掃描插入、BIST、JTAG/邊界掃描
• Familiarity with PD handoff flow and P&R feedback loops熟悉 PD 交接流程和佈局佈線回饋迴路
Technical Leadership Required
• Lead a team of 4–10 RTL designers across one or more IP blocks領導一個由 4-10 位 RTL 設計師組成的團隊,負責一個或多個 IP 模組
• Define and enforce RTL coding guidelines and review standards制定並執行 RTL 編碼規範和審查標準
• Mentor mid-level and junior engineers; conduct technical career development指導中級及初級工程師;進行技術職涯發展規劃
• Drive design schedule, milestone tracking, and risk identification推動設計進度、里程碑追蹤和風險識別
• Interface with DV, DFT, PD, and software teams — own design integration與設計驗證 (DV)、測試驗證 (DFT)、產品開發 (PD) 和軟體團隊對接—負責設計集成
• Represent RTL design in architecture reviews and cross-functional meetings代表 RTL 設計參與架構評審與跨職能會議
任職資格
• B.Sc in Electrical / Electronic Engineering or Computer Engineering; M.Sc preferred
• 3 or more successful ASIC tapeouts in a lead or senior contributor role
• Excellent written and verbal communication — able to author clear micro-arch specs
• Comfortable driving cross-team technical decisions under schedule pressure
• Strong debugging mindset: able to root-cause simulation failures and silicon bugs
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